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author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
commit | f3f3747431e001dc6c80da5b6489516b610c22d6 (patch) | |
tree | 24fcbc928df1619a82dbfd9ffa6d6f6809f509f6 /src/cpu/simple_thread.hh | |
parent | a54ae9f92b6000e8aaf5e056deaead8725c25a74 (diff) | |
download | gem5-f3f3747431e001dc6c80da5b6489516b610c22d6.tar.xz |
X86: Put in the foundation for x87 stack based fp registers.
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r-- | src/cpu/simple_thread.hh | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 1e87b0bb7..c018e3e49 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -235,52 +235,62 @@ class SimpleThread : public ThreadState // uint64_t readIntReg(int reg_idx) { - return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readIntReg(flatIndex); } FloatReg readFloatReg(int reg_idx, int width) { - return regs.readFloatReg(reg_idx, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatReg(flatIndex, width); } FloatReg readFloatReg(int reg_idx) { - return regs.readFloatReg(reg_idx); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatReg(flatIndex); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.readFloatRegBits(reg_idx, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatRegBits(flatIndex, width); } FloatRegBits readFloatRegBits(int reg_idx) { - return regs.readFloatRegBits(reg_idx); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatRegBits(flatIndex); } void setIntReg(int reg_idx, uint64_t val) { - regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setIntReg(flatIndex, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - regs.setFloatReg(reg_idx, val, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatReg(flatIndex, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - regs.setFloatReg(reg_idx, val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatReg(flatIndex, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.setFloatRegBits(reg_idx, val, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatRegBits(flatIndex, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.setFloatRegBits(reg_idx, val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatRegBits(flatIndex, val); } uint64_t readPC() |