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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commita480ba00b96f4c2e872f5a01bfa1782500f1066e (patch)
tree9d99a96528f37eb601f6e7268c3a359d84f02d57 /src/cpu/simple_thread.hh
parent0cb180ea0dcece9157ad71b4136d557c2dbcf209 (diff)
downloadgem5-a480ba00b96f4c2e872f5a01bfa1782500f1066e.tar.xz
Registers: Eliminate the ISA defined integer register file.
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 5e29fbb6d..97c02d7b8 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -36,6 +36,7 @@
#include "arch/isa_traits.hh"
#include "arch/regfile.hh"
#include "arch/tlb.hh"
+#include "arch/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
@@ -103,6 +104,7 @@ class SimpleThread : public ThreadState
FloatReg f[TheISA::NumFloatRegs];
FloatRegBits i[TheISA::NumFloatRegs];
} floatRegs;
+ TheISA::IntReg intRegs[TheISA::NumIntRegs];
TheISA::ISA isa; // one "instance" of the current ISA.
public:
@@ -230,6 +232,7 @@ class SimpleThread : public ThreadState
void clearArchRegs()
{
regs.clear();
+ memset(intRegs, 0, sizeof(intRegs));
memset(floatRegs.i, 0, sizeof(floatRegs.i));
}
@@ -239,7 +242,7 @@ class SimpleThread : public ThreadState
uint64_t readIntReg(int reg_idx)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
- return regs.readIntReg(flatIndex);
+ return intRegs[flatIndex];
}
FloatReg readFloatReg(int reg_idx)
@@ -257,7 +260,7 @@ class SimpleThread : public ThreadState
void setIntReg(int reg_idx, uint64_t val)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
- regs.setIntReg(flatIndex, val);
+ intRegs[flatIndex] = val;
}
void setFloatReg(int reg_idx, FloatReg val)