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| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/cpu/simple_thread.hh | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/simple_thread.hh')
| -rw-r--r-- | src/cpu/simple_thread.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 00355c602..5c52ba28d 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -255,11 +255,11 @@ class SimpleThread : public ThreadState } RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - RegVal regVal(readFloatRegBitsFlat(flatIndex)); + RegVal regVal(readFloatRegFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", reg_idx, flatIndex, regVal); return regVal; @@ -406,14 +406,14 @@ class SimpleThread : public ThreadState } void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); // XXX: Fix array out of bounds compiler error for gem5.fast // when checkercpu enabled if (flatIndex < TheISA::NumFloatRegs) - setFloatRegBitsFlat(flatIndex, val); + setFloatRegFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", reg_idx, flatIndex, val); } @@ -558,8 +558,8 @@ class SimpleThread : public ThreadState RegVal readIntRegFlat(int idx) { return intRegs[idx]; } void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } - RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } - void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } + RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; } + void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; } const VecRegContainer & readVecRegFlat(const RegIndex& reg) const |