cpu: Eliminate the ProxyThreadContext class.

Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.

Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.

Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 195 insertions, 135 deletions

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 53aa9d7b7..46f142f6f 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -83,9 +83,7 @@ namespace TheISA {
 /**
  * The SimpleThread object provides a combination of the ThreadState
  * object and the ThreadContext interface. It implements the
- * ThreadContext interface so that a ProxyThreadContext class can be
- * made using SimpleThread as the template parameter (see
- * thread_context.hh). It adds to the ThreadState object by adding all
+ * ThreadContext interface and adds to the ThreadState object by adding all
  * the objects needed for simple functional execution, including a
  * simple architectural register file, and pointers to the ITB and DTB
  * in full system mode. For CPU models that do not need more advanced
@@ -96,7 +94,7 @@ namespace TheISA {
  * examples.
  */
 
-class SimpleThread : public ThreadState
+class SimpleThread : public ThreadState, public ThreadContext
 {
   protected:
     typedef TheISA::MachInst MachInst;
@@ -124,11 +122,9 @@ class SimpleThread : public ThreadState
   public:
     std::string name() const
     {
-        return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
+        return csprintf("%s.[tid:%i]", baseCpu->name(), threadId());
     }
 
-    ProxyThreadContext<SimpleThread> *tc;
-
     System *system;
 
     BaseTLB *itb;
@@ -146,11 +142,11 @@ class SimpleThread : public ThreadState
                  Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
                  TheISA::ISA *_isa);
 
-    virtual ~SimpleThread();
+    virtual ~SimpleThread() {}
 
-    virtual void takeOverFrom(ThreadContext *oldContext);
+    void takeOverFrom(ThreadContext *oldContext) override;
 
-    void regStats(const std::string &name);
+    void regStats(const std::string &name) override;
 
     void copyState(ThreadContext *oldContext);
 
@@ -167,7 +163,7 @@ class SimpleThread : public ThreadState
      *  when a ThreadContext must be passed to objects outside of the
      *  CPU.
      */
-    ThreadContext *getTC() { return tc; }
+    ThreadContext *getTC() { return this; }
 
     void demapPage(Addr vaddr, uint64_t asn)
     {
@@ -185,7 +181,7 @@ class SimpleThread : public ThreadState
         dtb->demapPage(vaddr, asn);
     }
 
-    void dumpFuncProfile();
+    void dumpFuncProfile() override;
 
     Fault hwrei();
 
@@ -195,36 +191,86 @@ class SimpleThread : public ThreadState
      * ThreadContext interface functions.
      ******************************************/
 
-    BaseCPU *getCpuPtr() { return baseCpu; }
+    BaseCPU *getCpuPtr() override { return baseCpu; }
+
+    int cpuId() const override { return ThreadState::cpuId(); }
+    uint32_t socketId() const override { return ThreadState::socketId(); }
+    int threadId() const override { return ThreadState::threadId(); }
+    void setThreadId(int id) override { ThreadState::setThreadId(id); }
+    ContextID contextId() const override { return ThreadState::contextId(); }
+    void setContextId(ContextID id) override { ThreadState::setContextId(id); }
+
+    BaseTLB *getITBPtr() override { return itb; }
 
-    BaseTLB *getITBPtr() { return itb; }
+    BaseTLB *getDTBPtr() override { return dtb; }
 
-    BaseTLB *getDTBPtr() { return dtb; }
+    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
 
-    CheckerCPU *getCheckerCpuPtr() { return NULL; }
+    TheISA::ISA *getIsaPtr() override { return isa; }
 
-    TheISA::ISA *getIsaPtr() { return isa; }
+    TheISA::Decoder *getDecoderPtr() override { return &decoder; }
 
-    TheISA::Decoder *getDecoderPtr() { return &decoder; }
+    System *getSystemPtr() override { return system; }
+
+    TheISA::Kernel::Statistics *
+    getKernelStats()
+    {
+        return ThreadState::getKernelStats();
+    }
 
-    System *getSystemPtr() { return system; }
+    PortProxy &getPhysProxy() { return ThreadState::getPhysProxy(); }
+    FSTranslatingPortProxy &
+    getVirtProxy()
+    {
+        return ThreadState::getVirtProxy();
+    }
 
-    Status status() const { return _status; }
+    void initMemProxies(ThreadContext *tc) { ThreadState::initMemProxies(tc); }
+    SETranslatingPortProxy &
+    getMemProxy()
+    {
+        return ThreadState::getMemProxy();
+    }
 
-    void setStatus(Status newStatus) { _status = newStatus; }
+    Process *getProcessPtr() { return ThreadState::getProcessPtr(); }
+    void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); }
+
+    Status status() const override { return _status; }
+
+    void setStatus(Status newStatus) override { _status = newStatus; }
 
     /// Set the status to Active.
-    void activate();
+    void activate() override;
 
     /// Set the status to Suspended.
-    void suspend();
+    void suspend() override;
 
     /// Set the status to Halted.
-    void halt();
+    void halt() override;
 
-    void copyArchRegs(ThreadContext *tc);
+    EndQuiesceEvent *
+    getQuiesceEvent() override
+    {
+        return ThreadState::getQuiesceEvent();
+    }
 
-    void clearArchRegs()
+    Tick
+    readLastActivate() override
+    {
+        return ThreadState::readLastActivate();
+    }
+    Tick
+    readLastSuspend() override
+    {
+        return ThreadState::readLastSuspend();
+    }
+
+    void profileClear() override { ThreadState::profileClear(); }
+    void profileSample() override { ThreadState::profileSample(); }
+
+    void copyArchRegs(ThreadContext *tc) override;
+
+    void clearArchRegs() override
     {
         _pcState = 0;
         memset(intRegs, 0, sizeof(intRegs));
@@ -245,7 +291,7 @@ class SimpleThread : public ThreadState
     // New accessors for new decoder.
     //
     RegVal
-    readIntReg(int reg_idx)
+    readIntReg(RegIndex reg_idx) const override
     {
         int flatIndex = isa->flattenIntIndex(reg_idx);
         assert(flatIndex < TheISA::NumIntRegs);
@@ -256,7 +302,7 @@ class SimpleThread : public ThreadState
     }
 
     RegVal
-    readFloatReg(int reg_idx)
+    readFloatReg(RegIndex reg_idx) const override
     {
         int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
@@ -267,7 +313,7 @@ class SimpleThread : public ThreadState
     }
 
     const VecRegContainer&
-    readVecReg(const RegId& reg) const
+    readVecReg(const RegId& reg) const override
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -278,7 +324,7 @@ class SimpleThread : public ThreadState
     }
 
     VecRegContainer&
-    getWritableVecReg(const RegId& reg)
+    getWritableVecReg(const RegId& reg) override
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -305,27 +351,36 @@ class SimpleThread : public ThreadState
 
     /** Reads source vector 8bit operand. */
     virtual ConstVecLane8
-    readVec8BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint8_t>(reg); }
+    readVec8BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint8_t>(reg);
+    }
 
     /** Reads source vector 16bit operand. */
     virtual ConstVecLane16
-    readVec16BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint16_t>(reg); }
+    readVec16BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint16_t>(reg);
+    }
 
     /** Reads source vector 32bit operand. */
     virtual ConstVecLane32
-    readVec32BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint32_t>(reg); }
+    readVec32BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint32_t>(reg);
+    }
 
     /** Reads source vector 64bit operand. */
     virtual ConstVecLane64
-    readVec64BitLaneReg(const RegId& reg) const
-    { return readVecLane<uint64_t>(reg); }
+    readVec64BitLaneReg(const RegId &reg) const override
+    {
+        return readVecLane<uint64_t>(reg);
+    }
 
     /** Write a lane of the destination vector register. */
     template <typename LD>
-    void setVecLaneT(const RegId& reg, const LD& val)
+    void
+    setVecLaneT(const RegId &reg, const LD &val)
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -333,21 +388,33 @@ class SimpleThread : public ThreadState
         DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
                 reg.index(), flatIndex, reg.elemIndex(), val);
     }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val)
-    { return setVecLaneT(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val)
-    { return setVecLaneT(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val)
-    { return setVecLaneT(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val)
-    { return setVecLaneT(reg, val); }
+    virtual void
+    setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::TwoByte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::FourByte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::EightByte> &val) override
+    {
+        return setVecLaneT(reg, val);
+    }
     /** @} */
 
-    const VecElem& readVecElem(const RegId& reg) const
+    const VecElem &
+    readVecElem(const RegId &reg) const override
     {
         int flatIndex = isa->flattenVecElemIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -357,8 +424,8 @@ class SimpleThread : public ThreadState
         return regVal;
     }
 
-    const VecPredRegContainer&
-    readVecPredReg(const RegId& reg) const
+    const VecPredRegContainer &
+    readVecPredReg(const RegId &reg) const override
     {
         int flatIndex = isa->flattenVecPredIndex(reg.index());
         assert(flatIndex < TheISA::NumVecPredRegs);
@@ -368,8 +435,8 @@ class SimpleThread : public ThreadState
         return regVal;
     }
 
-    VecPredRegContainer&
-    getWritableVecPredReg(const RegId& reg)
+    VecPredRegContainer &
+    getWritableVecPredReg(const RegId &reg) override
     {
         int flatIndex = isa->flattenVecPredIndex(reg.index());
         assert(flatIndex < TheISA::NumVecPredRegs);
@@ -381,7 +448,7 @@ class SimpleThread : public ThreadState
     }
 
     RegVal
-    readCCReg(int reg_idx)
+    readCCReg(RegIndex reg_idx) const override
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -398,7 +465,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setIntReg(int reg_idx, RegVal val)
+    setIntReg(RegIndex reg_idx, RegVal val) override
     {
         int flatIndex = isa->flattenIntIndex(reg_idx);
         assert(flatIndex < TheISA::NumIntRegs);
@@ -408,7 +475,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setFloatReg(int reg_idx, RegVal val)
+    setFloatReg(RegIndex reg_idx, RegVal val) override
     {
         int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
@@ -421,7 +488,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setVecReg(const RegId& reg, const VecRegContainer& val)
+    setVecReg(const RegId &reg, const VecRegContainer &val) override
     {
         int flatIndex = isa->flattenVecIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -431,7 +498,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setVecElem(const RegId& reg, const VecElem& val)
+    setVecElem(const RegId &reg, const VecElem &val) override
     {
         int flatIndex = isa->flattenVecElemIndex(reg.index());
         assert(flatIndex < TheISA::NumVecRegs);
@@ -441,7 +508,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
+    setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
     {
         int flatIndex = isa->flattenVecPredIndex(reg.index());
         assert(flatIndex < TheISA::NumVecPredRegs);
@@ -451,7 +518,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setCCReg(int reg_idx, RegVal val)
+    setCCReg(RegIndex reg_idx, RegVal val) override
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -464,174 +531,167 @@ class SimpleThread : public ThreadState
 #endif
     }
 
-    TheISA::PCState
-    pcState()
-    {
-        return _pcState;
-    }
+    TheISA::PCState pcState() const override { return _pcState; }
+    void pcState(const TheISA::PCState &val) override { _pcState = val; }
 
     void
-    pcState(const TheISA::PCState &val)
+    pcStateNoRecord(const TheISA::PCState &val) override
     {
         _pcState = val;
     }
 
-    void
-    pcStateNoRecord(const TheISA::PCState &val)
-    {
-        _pcState = val;
-    }
+    Addr instAddr() const override  { return _pcState.instAddr(); }
+    Addr nextInstAddr() const override { return _pcState.nextInstAddr(); }
+    MicroPC microPC() const override { return _pcState.microPC(); }
+    bool readPredicate() const { return predicate; }
+    void setPredicate(bool val) { predicate = val; }
 
-    Addr
-    instAddr()
+    RegVal
+    readMiscRegNoEffect(RegIndex misc_reg) const override
     {
-        return _pcState.instAddr();
+        return isa->readMiscRegNoEffect(misc_reg);
     }
 
-    Addr
-    nextInstAddr()
+    RegVal
+    readMiscReg(RegIndex misc_reg) override
     {
-        return _pcState.nextInstAddr();
+        return isa->readMiscReg(misc_reg, this);
     }
 
     void
-    setNPC(Addr val)
+    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
     {
-        _pcState.setNPC(val);
+        return isa->setMiscRegNoEffect(misc_reg, val);
     }
 
-    MicroPC
-    microPC()
+    void
+    setMiscReg(RegIndex misc_reg, RegVal val) override
     {
-        return _pcState.microPC();
+        return isa->setMiscReg(misc_reg, val, this);
     }
 
-    bool readPredicate()
+    RegId
+    flattenRegId(const RegId& regId) const override
     {
-        return predicate;
+        return isa->flattenRegId(regId);
     }
 
-    void setPredicate(bool val)
-    {
-        predicate = val;
-    }
+    unsigned readStCondFailures() const override { return storeCondFailures; }
 
-    RegVal
-    readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
+    void
+    setStCondFailures(unsigned sc_failures) override
     {
-        return isa->readMiscRegNoEffect(misc_reg);
+        storeCondFailures = sc_failures;
     }
 
-    RegVal
-    readMiscReg(int misc_reg, ThreadID tid=0)
+    Counter
+    readFuncExeInst() const override
     {
-        return isa->readMiscReg(misc_reg, tc);
+        return ThreadState::readFuncExeInst();
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
+    syscall(int64_t callnum, Fault *fault) override
     {
-        return isa->setMiscRegNoEffect(misc_reg, val);
+        process->syscall(callnum, this, fault);
     }
 
+    RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; }
     void
-    setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
+    setIntRegFlat(RegIndex idx, RegVal val) override
     {
-        return isa->setMiscReg(misc_reg, val, tc);
+        intRegs[idx] = val;
     }
 
-    RegId
-    flattenRegId(const RegId& regId) const
+    RegVal
+    readFloatRegFlat(RegIndex idx) const override
     {
-        return isa->flattenRegId(regId);
+        return floatRegs[idx];
     }
-
-    unsigned readStCondFailures() { return storeCondFailures; }
-
-    void setStCondFailures(unsigned sc_failures)
-    { storeCondFailures = sc_failures; }
-
     void
-    syscall(int64_t callnum, Fault *fault)
+    setFloatRegFlat(RegIndex idx, RegVal val) override
     {
-        process->syscall(callnum, tc, fault);
+        floatRegs[idx] = val;
     }
 
-    RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
-    void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }
-
-    RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; }
-    void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; }
-
     const VecRegContainer &
-    readVecRegFlat(const RegIndex& reg) const
+    readVecRegFlat(RegIndex reg) const override
     {
         return vecRegs[reg];
     }
 
     VecRegContainer &
-    getWritableVecRegFlat(const RegIndex& reg)
+    getWritableVecRegFlat(RegIndex reg) override
     {
         return vecRegs[reg];
     }
 
     void
-    setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
+    setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
     {
         vecRegs[reg] = val;
     }
 
     template <typename T>
     VecLaneT<T, true>
-    readVecLaneFlat(const RegIndex& reg, int lId) const
+    readVecLaneFlat(RegIndex reg, int lId) const
     {
         return vecRegs[reg].laneView<T>(lId);
     }
 
     template <typename LD>
     void
-    setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
+    setVecLaneFlat(RegIndex reg, int lId, const LD &val)
     {
         vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
     }
 
     const VecElem &
-    readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
+    readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
     {
         return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
     }
 
     void
-    setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
-                   const VecElem val)
+    setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
+                   const VecElem &val) override
     {
         vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
     }
 
-    const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const
+    const VecPredRegContainer &
+    readVecPredRegFlat(RegIndex reg) const override
     {
         return vecPredRegs[reg];
     }
 
-    VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg)
+    VecPredRegContainer &
+    getWritableVecPredRegFlat(RegIndex reg) override
     {
         return vecPredRegs[reg];
     }
 
-    void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val)
+    void
+    setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
     {
         vecPredRegs[reg] = val;
     }
 
 #ifdef ISA_HAS_CC_REGS
-    RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
-    void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
+    RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
+    void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
 #else
-    RegVal readCCRegFlat(int idx)
-    { panic("readCCRegFlat w/no CC regs!\n"); }
+    RegVal
+    readCCRegFlat(RegIndex idx) const override
+    {
+        panic("readCCRegFlat w/no CC regs!\n");
+    }
 
-    void setCCRegFlat(int idx, RegVal val)
-    { panic("setCCRegFlat w/no CC regs!\n"); }
+    void
+    setCCRegFlat(RegIndex idx, RegVal val) override
+    {
+        panic("setCCRegFlat w/no CC regs!\n");
+    }
 #endif
 };