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| author | Geoffrey Blake <Geoffrey.Blake@arm.com> | 2013-10-17 10:20:45 -0500 |
|---|---|---|
| committer | Geoffrey Blake <Geoffrey.Blake@arm.com> | 2013-10-17 10:20:45 -0500 |
| commit | 3d582c767a2891d4a4ab8defa8929b061cbcee18 (patch) | |
| tree | 835656c3df08fd9b7ccf7216f5f11985671f990b /src/cpu/static_inst.cc | |
| parent | ad614bf24da852ecd28c03a5bcb72ecd24b37238 (diff) | |
| download | gem5-3d582c767a2891d4a4ab8defa8929b061cbcee18.tar.xz | |
config: Fix for port references generated multiple times
SimObjects are expected to only generate one port reference per
port belonging to them. There is a subtle bug with using "not"
here as a VectorPort is seen as not having a reference if it is
either None or empty as per Python docs sec 9.9 for Standard operators.
Intended behavior is to only check if we have not created the reference.
Diffstat (limited to 'src/cpu/static_inst.cc')
0 files changed, 0 insertions, 0 deletions