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authorKevin Lim <ktlim@umich.edu>2006-05-31 11:34:42 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-31 11:34:42 -0400
commitd4b73086b6b0856c28433b55c8dd5c7b56a1b6df (patch)
treeb54cb10579c6c5788fc09e7abd5d3a0ab1dd533c /src/cpu/static_inst.hh
parentd77d39daee5c3ba8483d58911a1d5b12c4707040 (diff)
parent4a5b51b516853c9fcaabc44caacdd7e8e93dc0ef (diff)
downloadgem5-d4b73086b6b0856c28433b55c8dd5c7b56a1b6df.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem --HG-- extra : convert_revision : 3d951bbeee0178de47e1bdbe704808544bfe732e
Diffstat (limited to 'src/cpu/static_inst.hh')
-rw-r--r--src/cpu/static_inst.hh15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 33c9144fb..803b7a09b 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -41,6 +41,8 @@
// forward declarations
struct AlphaSimpleImpl;
+struct OzoneImpl;
+struct SimpleImpl;
class ExecContext;
class DynInst;
class Packet;
@@ -48,6 +50,10 @@ class Packet;
template <class Impl>
class AlphaDynInst;
+template <class Impl>
+class OzoneDynInst;
+
+class CheckerCPU;
class FastCPU;
class AtomicSimpleCPU;
class TimingSimpleCPU;
@@ -100,6 +106,7 @@ class StaticInstBase : public RefCounted
IsMemRef, ///< References memory (load, store, or prefetch).
IsLoad, ///< Reads from memory (load or prefetch).
IsStore, ///< Writes to memory.
+ IsStoreConditional, ///< Store conditional instruction.
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
IsCopy, ///< Fast Cache block copy
@@ -124,6 +131,10 @@ class StaticInstBase : public RefCounted
IsWriteBarrier, ///< Is a write barrier
IsNonSpeculative, ///< Should not be executed speculatively
+ IsQuiesce, ///< Is a quiesce instruction
+
+ IsIprAccess, ///< Accesses IPRs
+ IsUnverifiable, ///< Can't be verified by a checker
NumFlags
};
@@ -187,6 +198,7 @@ class StaticInstBase : public RefCounted
bool isMemRef() const { return flags[IsMemRef]; }
bool isLoad() const { return flags[IsLoad]; }
bool isStore() const { return flags[IsStore]; }
+ bool isStoreConditional() const { return flags[IsStoreConditional]; }
bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
bool isCopy() const { return flags[IsCopy];}
@@ -211,6 +223,9 @@ class StaticInstBase : public RefCounted
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
+ bool isQuiesce() const { return flags[IsQuiesce]; }
+ bool isIprAccess() const { return flags[IsIprAccess]; }
+ bool isUnverifiable() const { return flags[IsUnverifiable]; }
//@}
/// Operation class. Used to select appropriate function unit in issue.