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authorKorey Sewell <ksewell@umich.edu>2006-07-06 11:25:44 -0400
committerKorey Sewell <ksewell@umich.edu>2006-07-06 11:25:44 -0400
commit215041215b06f330d072b0537d7fe70739b4927d (patch)
tree8676c6d3f746d027561ee2fd4761253dd934e27d /src/cpu/static_inst.hh
parentf4c5609988731f52f9c5bd84ee2db364bbf6fd97 (diff)
downloadgem5-215041215b06f330d072b0537d7fe70739b4927d.tar.xz
more steps toward O3 SMT
src/arch/mips/isa/formats/fp.isa: Adjust for newmem src/cpu/cpu_models.py: Use O3DynInst instead of convoluted way src/cpu/o3/alpha/impl.hh: take out O3DynInst typedef here ... src/cpu/o3/cpu.cc: open up the SMT functions in the O3CPU src/cpu/static_inst.hh: Add O3DynInst src/cpu/o3/dyn_inst.hh: Use to get ISA-specific O3DynInst --HG-- extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
Diffstat (limited to 'src/cpu/static_inst.hh')
-rw-r--r--src/cpu/static_inst.hh2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index a98078634..19f06f669 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -53,6 +53,8 @@ class Packet;
template <class Impl>
class AlphaDynInst;
+//class O3DynInst;
+
template <class Impl>
class OzoneDynInst;