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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/static_inst.hh | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/static_inst.hh')
| -rw-r--r-- | src/cpu/static_inst.hh | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 684a22856..751301095 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -42,6 +42,7 @@ #include "base/types.hh" #include "config/the_isa.hh" #include "cpu/op_class.hh" +#include "cpu/reg_class.hh" #include "cpu/static_inst_fwd.hh" #include "cpu/thread_context.hh" #include "enums/StaticInstFlags.hh" @@ -70,8 +71,6 @@ class StaticInst : public RefCounted, public StaticInstFlags public: /// Binary extended machine instruction type. typedef TheISA::ExtMachInst ExtMachInst; - /// Logical register index type. - typedef TheISA::RegIndex RegIndex; enum { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs @@ -185,11 +184,11 @@ class StaticInst : public RefCounted, public StaticInstFlags /// Return logical index (architectural reg num) of i'th destination reg. /// Only the entries from 0 through numDestRegs()-1 are valid. - RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } + RegId destRegIdx(int i) const { return _destRegIdx[i]; } /// Return logical index (architectural reg num) of i'th source reg. /// Only the entries from 0 through numSrcRegs()-1 are valid. - RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } + RegId srcRegIdx(int i) const { return _srcRegIdx[i]; } /// Pointer to a statically allocated "null" instruction object. /// Used to give eaCompInst() and memAccInst() something to return @@ -220,9 +219,9 @@ class StaticInst : public RefCounted, public StaticInstFlags protected: /// See destRegIdx(). - RegIndex _destRegIdx[MaxInstDestRegs]; + RegId _destRegIdx[MaxInstDestRegs]; /// See srcRegIdx(). - RegIndex _srcRegIdx[MaxInstSrcRegs]; + RegId _srcRegIdx[MaxInstSrcRegs]; /** * Base mnemonic (e.g., "add"). Used by generateDisassembly() |