MEM: Add the PortId type and a corresponding id field to Port

This patch introduces the PortId type, moves the definition of
INVALID_PORT_ID to the Port class, and also gives every port an id to
reflect the fact that each element in a vector port has an
identifier/index.

Previously the bus and Ruby testers (and potentially other users of
the vector ports) added the id field in their port subclasses, and now
this functionality is always present as it is moved to the base class.

1 files changed, 2 insertions, 4 deletions

diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index bd0b52a90..08b034d3f 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -54,12 +54,10 @@ class RubyDirectedTester : public MemObject
 
       public:
         CpuPort(const std::string &_name, RubyDirectedTester *_tester,
-                uint32_t _idx)
-            : MasterPort(_name, _tester), tester(_tester), idx(_idx)
+                Port::PortId _id)
+            : MasterPort(_name, _tester, _id), tester(_tester)
         {}
 
-        uint32_t idx;
-
       protected:
         virtual bool recvTiming(PacketPtr pkt);
         virtual void recvRetry()