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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-03 07:42:54 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-03 07:42:54 -0400
commit2698e739660516af442c0f913eb0e91a00e7b7db (patch)
tree331dfa865e3b36d5187353fe3db57f93c73eb0e0 /src/cpu/testers/directedtest
parent1ff4c45bbbaa22d5bd91e9bdd34d4435290ab8be (diff)
downloadgem5-2698e739660516af442c0f913eb0e91a00e7b7db.tar.xz
base: Use the global Mersenne twister throughout
This patch tidies up random number generation to ensure that it is done consistently throughout the code base. In essence this involves a clean-up of Ruby, and some code simplifications in the traffic generator. As part of this patch a bunch of skewed distributions (off-by-one etc) have been fixed. Note that a single global random number generator is used, and that the object instantiation order will impact the behaviour (the sequence of numbers will be unaffected, but if module A calles random before module B then they would obviously see a different outcome). The dependency on the instantiation order is true in any case due to the execution-model of gem5, so we leave it as is. Also note that the global ranom generator is not thread safe at this point. Regressions using the memtest, TrafficGen or any Ruby tester are affected and will be updated accordingly.
Diffstat (limited to 'src/cpu/testers/directedtest')
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index f4bb578e3..80523280b 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -27,6 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "base/random.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
@@ -60,7 +61,7 @@ SeriesRequestGenerator::initiate()
Request *req = new Request(m_address, 1, flags, masterId);
Packet::Command cmd;
- bool do_write = ((random() % 100) < m_percent_writes);
+ bool do_write = (random_mt.random(0, 100) < m_percent_writes);
if (do_write) {
cmd = MemCmd::WriteReq;
} else {