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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-13 06:43:09 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-13 06:43:09 -0500
commit5a9a743cfc4517f93e5c94533efa767b92272c59 (patch)
treef3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /src/cpu/testers/directedtest
parent8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff)
downloadgem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'src/cpu/testers/directedtest')
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index ccadc5b36..bf3eace08 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -48,6 +48,6 @@ class InvalidateGenerator(DirectedGenerator):
class RubyDirectedTester(MemObject):
type = 'RubyDirectedTester'
- cpuPort = VectorPort("the cpu ports")
+ cpuPort = VectorMasterPort("the cpu ports")
requests_to_complete = Param.Int("checks to complete")
generator = Param.DirectedGenerator("the request generator")