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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
| commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
| tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/testers/directedtest | |
| parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
| download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz | |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/testers/directedtest')
5 files changed, 7 insertions, 3 deletions
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc index 68ea55449..d69261cf0 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.cc +++ b/src/cpu/testers/directedtest/DirectedGenerator.cc @@ -28,9 +28,11 @@ */ #include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "sim/system.hh" DirectedGenerator::DirectedGenerator(const Params *p) - : SimObject(p) + : SimObject(p), + masterId(p->system->getMasterId(name())) { m_num_cpus = p->num_cpus; m_directed_tester = NULL; diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh index c156efff0..422a0ddb6 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.hh +++ b/src/cpu/testers/directedtest/DirectedGenerator.hh @@ -49,6 +49,7 @@ class DirectedGenerator : public SimObject protected: int m_num_cpus; + MasterID masterId; RubyDirectedTester* m_directed_tester; }; diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index 4d8271a05..f01e6fb50 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -58,7 +58,7 @@ InvalidateGenerator::initiate() Packet::Command cmd; // For simplicity, requests are assumed to be 1 byte-sized - Request *req = new Request(m_address, 1, flags); + Request *req = new Request(m_address, 1, flags, masterId); // // Based on the current state, issue a load or a store diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index af1970594..ccadc5b36 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -35,6 +35,7 @@ class DirectedGenerator(SimObject): type = 'DirectedGenerator' abstract = True num_cpus = Param.Int("num of cpus") + system = Param.System(Parent.any, "System we belong to") class SeriesRequestGenerator(DirectedGenerator): type = 'SeriesRequestGenerator' diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index 4cf9aed1c..137d24b21 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -59,7 +59,7 @@ SeriesRequestGenerator::initiate() Request::Flags flags; // For simplicity, requests are assumed to be 1 byte-sized - Request *req = new Request(m_address, 1, flags); + Request *req = new Request(m_address, 1, flags, masterId); Packet::Command cmd; if (m_issue_writes) { |