diff options
| author | Gabe Black <gabeblack@google.com> | 2019-04-22 19:45:10 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-04-28 01:19:40 +0000 |
| commit | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch) | |
| tree | 893cea35432466600b55a2e4434ed61ba1e28f69 /src/cpu/testers/directedtest | |
| parent | 3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff) | |
| download | gem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz | |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/testers/directedtest')
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.cc | 4 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.hh | 7 | ||||
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.py | 4 |
3 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index cd367b498..afe2b1447 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -47,7 +47,7 @@ #include "sim/sim_exit.hh" RubyDirectedTester::RubyDirectedTester(const Params *p) - : MemObject(p), + : ClockedObject(p), directedStartEvent([this]{ wakeup(); }, "Directed tick", false, Event::CPU_Tick_Pri), m_requests_to_complete(p->requests_to_complete), @@ -83,7 +83,7 @@ RubyDirectedTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } else { if (idx >= static_cast<int>(ports.size())) { panic("RubyDirectedTester::getPort: unknown index %d\n", idx); diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 740843562..f0c694e82 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -34,16 +34,17 @@ #include <string> #include <vector> +#include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/DataBlock.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/common/TypeDefines.hh" -#include "mem/mem_object.hh" -#include "mem/packet.hh" #include "params/RubyDirectedTester.hh" +#include "sim/clocked_object.hh" class DirectedGenerator; -class RubyDirectedTester : public MemObject +class RubyDirectedTester : public ClockedObject { public: class CpuPort : public MasterPort diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index 9f90c9b41..5b513e42e 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -30,7 +30,7 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject class DirectedGenerator(SimObject): type = 'DirectedGenerator' @@ -52,7 +52,7 @@ class InvalidateGenerator(DirectedGenerator): cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") -class RubyDirectedTester(MemObject): +class RubyDirectedTester(ClockedObject): type = 'RubyDirectedTester' cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" cpuPort = VectorMasterPort("the cpu ports") |