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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
| commit | 5a9a743cfc4517f93e5c94533efa767b92272c59 (patch) | |
| tree | f3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /src/cpu/testers/memtest | |
| parent | 8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff) | |
| download | gem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz | |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.
Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'src/cpu/testers/memtest')
| -rw-r--r-- | src/cpu/testers/memtest/MemTest.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 6a3568379..1b4d6767c 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -48,8 +48,9 @@ class MemTest(MemObject): "progress report interval (in accesses)") trace_addr = Param.Addr(0, "address to trace") - test = Port("Port to the memory system to test") - functional = Port("Port to the functional memory used for verification") + test = MasterPort("Port to the memory system to test") + functional = MasterPort("Port to the functional memory " \ + "used for verification") suppress_func_warnings = Param.Bool(False, "suppress warnings when functional accesses fail.\n") sys = Param.System(Parent.any, "System Parameter") |