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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:38 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:38 -0600
commit8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch)
tree0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/testers/memtest
parent7e104a1af235823e3d641a972ea920937f7ec67d (diff)
downloadgem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/testers/memtest')
-rw-r--r--src/cpu/testers/memtest/MemTest.py2
-rw-r--r--src/cpu/testers/memtest/memtest.cc6
-rw-r--r--src/cpu/testers/memtest/memtest.hh3
3 files changed, 9 insertions, 2 deletions
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index d5f456d69..6a3568379 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -52,3 +52,5 @@ class MemTest(MemObject):
functional = Port("Port to the functional memory used for verification")
suppress_func_warnings = Param.Bool(False,
"suppress warnings when functional accesses fail.\n")
+ sys = Param.System(Parent.any, "System Parameter")
+
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index d70dc96e6..2d0131a92 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -46,6 +46,7 @@
#include "mem/request.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
+#include "sim/system.hh"
using namespace std;
@@ -132,6 +133,7 @@ MemTest::MemTest(const Params *p)
percentFunctional(p->percent_functional),
percentUncacheable(p->percent_uncacheable),
issueDmas(p->issue_dmas),
+ masterId(p->sys->getMasterId(name())),
progressInterval(p->progress_interval),
nextProgressMessage(p->progress_interval),
percentSourceUnaligned(p->percent_source_unaligned),
@@ -321,11 +323,11 @@ MemTest::tick()
if (issueDmas) {
paddr &= ~((1 << dma_access_size) - 1);
- req->setPhys(paddr, 1 << dma_access_size, flags);
+ req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
req->setThreadContext(id,0);
} else {
paddr &= ~((1 << access_size) - 1);
- req->setPhys(paddr, 1 << access_size, flags);
+ req->setPhys(paddr, 1 << access_size, flags, masterId);
req->setThreadContext(id,0);
}
assert(req->getSize() == 1);
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index 1a59914fd..208b34caf 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -138,6 +138,9 @@ class MemTest : public MemObject
bool issueDmas;
+ /** Request id for all generated traffic */
+ MasterID masterId;
+
int id;
std::set<unsigned> outstandingAddrs;