MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

2 files changed, 9 insertions, 15 deletions

diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index dffaa71ed..07cdf73a6 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -85,11 +85,6 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
 }
 
 void
-MemTest::CpuPort::recvRangeChange()
-{
-}
-
-void
 MemTest::CpuPort::recvRetry()
 {
     memtest->doRetry();
@@ -161,15 +156,15 @@ MemTest::MemTest(const Params *p)
     dmaOutstanding = false;
 }
 
-Port *
-MemTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+MemTest::getMasterPort(const std::string &if_name, int idx)
 {
     if (if_name == "functional")
-        return &funcPort;
+        return funcPort;
     else if (if_name == "test")
-        return &cachePort;
+        return cachePort;
     else
-        panic("No Such Port\n");
+        return MemObject::getMasterPort(if_name, idx);
 }
 
 void
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index c56a37574..d179fa530 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -62,7 +62,8 @@ class MemTest : public MemObject
     // main simulation loop (one cycle)
     void tick();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
     /**
      * Print state of address in memory system via PrintReq (for
@@ -84,14 +85,14 @@ class MemTest : public MemObject
 
     TickEvent tickEvent;
 
-    class CpuPort : public Port
+    class CpuPort : public MasterPort
     {
         MemTest *memtest;
 
       public:
 
         CpuPort(const std::string &_name, MemTest *_memtest)
-            : Port(_name, _memtest), memtest(_memtest)
+            : MasterPort(_name, _memtest), memtest(_memtest)
         { }
 
       protected:
@@ -102,8 +103,6 @@ class MemTest : public MemObject
 
         virtual void recvFunctional(PacketPtr pkt);
 
-        virtual void recvRangeChange();
-
         virtual void recvRetry();
     };