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authorAndreas Hansson <andreas.hansson@arm.com>2012-04-25 10:41:23 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-04-25 10:41:23 -0400
commit4c92708b48d51bfb6592ff48925f5a7a0157da5b (patch)
tree2535fb1529ef60f64a3f26f943af5d8d681b22d8 /src/cpu/testers/rubytest/RubyTester.hh
parent79750fc575db0966ff9d0530975377c35f630eca (diff)
downloadgem5-4c92708b48d51bfb6592ff48925f5a7a0157da5b.tar.xz
MEM: Add the PortId type and a corresponding id field to Port
This patch introduces the PortId type, moves the definition of INVALID_PORT_ID to the Port class, and also gives every port an id to reflect the fact that each element in a vector port has an identifier/index. Previously the bus and Ruby testers (and potentially other users of the vector ports) added the id field in their port subclasses, and now this functionality is always present as it is moved to the base class.
Diffstat (limited to 'src/cpu/testers/rubytest/RubyTester.hh')
-rw-r--r--src/cpu/testers/rubytest/RubyTester.hh6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 266209b8f..5d2202f65 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -57,12 +57,10 @@ class RubyTester : public MemObject
// RubyPorts that support both types of requests, separate InstOnly
// and DataOnly CpuPorts will map to that RubyPort
- CpuPort(const std::string &_name, RubyTester *_tester, int _idx)
- : MasterPort(_name, _tester), tester(_tester), idx(_idx)
+ CpuPort(const std::string &_name, RubyTester *_tester, PortId _id)
+ : MasterPort(_name, _tester, _id), tester(_tester)
{}
- int idx;
-
protected:
virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry()