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authorGabe Black <gabeblack@google.com>2019-04-22 19:45:10 -0700
committerGabe Black <gabeblack@google.com>2019-04-28 01:19:40 +0000
commitcdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch)
tree893cea35432466600b55a2e4434ed61ba1e28f69 /src/cpu/testers/rubytest
parent3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff)
downloadgem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/testers/rubytest')
-rw-r--r--src/cpu/testers/rubytest/RubyTester.cc4
-rw-r--r--src/cpu/testers/rubytest/RubyTester.hh5
-rw-r--r--src/cpu/testers/rubytest/RubyTester.py4
3 files changed, 7 insertions, 6 deletions
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index cb23688c4..30af47586 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -50,7 +50,7 @@
#include "sim/system.hh"
RubyTester::RubyTester(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
false, Event::CPU_Tick_Pri),
_masterId(p->system->getMasterId(this)),
@@ -134,7 +134,7 @@ RubyTester::getPort(const std::string &if_name, PortID idx)
if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
if_name != "cpuDataPort") {
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
} else {
if (if_name == "cpuInstPort") {
if (idx > m_num_inst_only_ports) {
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 3ca71f608..4ac553b4c 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -47,13 +47,14 @@
#include <vector>
#include "cpu/testers/rubytest/CheckTable.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
+#include "mem/port.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "params/RubyTester.hh"
+#include "sim/clocked_object.hh"
-class RubyTester : public MemObject
+class RubyTester : public ClockedObject
{
public:
class CpuPort : public MasterPort
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index 2ac1697fd..ecf52b668 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -28,9 +28,9 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class RubyTester(MemObject):
+class RubyTester(ClockedObject):
type = 'RubyTester'
cxx_header = "cpu/testers/rubytest/RubyTester.hh"
num_cpus = Param.Int("number of cpus / RubyPorts")