cpu: Allow creation of traffic gen from generic SimObjects

This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.

Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 9 insertions, 7 deletions

diff --git a/src/cpu/testers/traffic_gen/base_gen.hh b/src/cpu/testers/traffic_gen/base_gen.hh
index b7c3363ff..74b8bbd45 100644
--- a/src/cpu/testers/traffic_gen/base_gen.hh
+++ b/src/cpu/testers/traffic_gen/base_gen.hh
@@ -70,9 +70,6 @@ class BaseGen
     /** The MasterID used for generating requests */
     const MasterID masterID;
 
-    /** Cache line size in the simulated system */
-    const Addr cacheLineSize;
-
     /**
      * Generate a new request and associated packet
      *
@@ -92,11 +89,11 @@ class BaseGen
     /**
      * Create a base generator.
      *
-     * @param _name Name to use for status and debug
+     * @param obj simobject owning the generator
      * @param master_id MasterID set on each request
      * @param _duration duration of this state before transitioning
      */
-    BaseGen(BaseTrafficGen &gen, Tick _duration);
+    BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
 
     virtual ~BaseGen() { }
 
@@ -140,8 +137,10 @@ class BaseGen
 class StochasticGen : public BaseGen
 {
   public:
-    StochasticGen(BaseTrafficGen &gen, Tick _duration,
-                  Addr start_addr, Addr end_addr, Addr _blocksize,
+    StochasticGen(SimObject &obj,
+                  MasterID master_id, Tick _duration,
+                  Addr start_addr, Addr end_addr,
+                  Addr _blocksize, Addr cacheline_size,
                   Tick min_period, Tick max_period,
                   uint8_t read_percent, Addr data_limit);
 
@@ -155,6 +154,9 @@ class StochasticGen : public BaseGen
     /** Blocksize and address increment */
     const Addr blocksize;
 
+    /** Cache line size in the simulated system */
+    const Addr cacheLineSize;
+
     /** Request generation period */
     const Tick minPeriod;
     const Tick maxPeriod;