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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-07-18 14:28:21 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-07-25 16:47:15 +0000 |
| commit | a327a6763a356dc386c0f273fe091784a20b495a (patch) | |
| tree | ac7f4ef68fee25df16f5019f84f43d843f4105a6 /src/cpu/testers/traffic_gen/dram_gen.cc | |
| parent | 2fe3d660260e7b546b5860ac4459014ed9bee907 (diff) | |
| download | gem5-a327a6763a356dc386c0f273fe091784a20b495a.tar.xz | |
cpu: Allow creation of traffic gen from generic SimObjects
This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.
Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/testers/traffic_gen/dram_gen.cc')
| -rw-r--r-- | src/cpu/testers/traffic_gen/dram_gen.cc | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/cpu/testers/traffic_gen/dram_gen.cc b/src/cpu/testers/traffic_gen/dram_gen.cc index fb8212694..d061f6cab 100644 --- a/src/cpu/testers/traffic_gen/dram_gen.cc +++ b/src/cpu/testers/traffic_gen/dram_gen.cc @@ -49,8 +49,10 @@ #include "debug/TrafficGen.hh" -DramGen::DramGen(BaseTrafficGen &gen, Tick _duration, - Addr start_addr, Addr end_addr, Addr _blocksize, +DramGen::DramGen(SimObject &obj, + MasterID master_id, Tick _duration, + Addr start_addr, Addr end_addr, + Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, @@ -58,8 +60,9 @@ DramGen::DramGen(BaseTrafficGen &gen, Tick _duration, unsigned int nbr_of_banks_util, unsigned int addr_mapping, unsigned int nbr_of_ranks) - : RandomGen(gen, _duration, start_addr, end_addr, - _blocksize, min_period, max_period, read_percent, data_limit), + : RandomGen(obj, master_id, _duration, start_addr, end_addr, + _blocksize, cacheline_size, min_period, max_period, + read_percent, data_limit), numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0), isRead(true), pageSize(page_size), pageBits(floorLog2(page_size / _blocksize)), |