cpu: Allow creation of traffic gen from generic SimObjects

This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.

Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 7 insertions, 3 deletions

diff --git a/src/cpu/testers/traffic_gen/dram_gen.hh b/src/cpu/testers/traffic_gen/dram_gen.hh
index 6809c3bf2..8b9efb747 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_gen.hh
@@ -67,11 +67,13 @@ class DramGen : public RandomGen
     /**
      * Create a DRAM address sequence generator.
      *
-     * @param gen Traffic generator owning this sequence generator
+     * @param obj SimObject owning this sequence generator
+     * @param master_id MasterID related to the memory requests
      * @param _duration duration of this state before transitioning
      * @param start_addr Start address
      * @param end_addr End address
      * @param _blocksize Size used for transactions injected
+     * @param cacheline_size cache line size in the system
      * @param min_period Lower limit of random inter-transaction time
      * @param max_period Upper limit of random inter-transaction time
      * @param read_percent Percent of transactions that are reads
@@ -85,8 +87,10 @@ class DramGen : public RandomGen
      *                     0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
      *                     assumes single channel system
      */
-    DramGen(BaseTrafficGen &gen, Tick _duration,
-            Addr start_addr, Addr end_addr, Addr _blocksize,
+    DramGen(SimObject &obj,
+            MasterID master_id, Tick _duration,
+            Addr start_addr, Addr end_addr,
+            Addr _blocksize, Addr cacheline_size,
             Tick min_period, Tick max_period,
             uint8_t read_percent, Addr data_limit,
             unsigned int num_seq_pkts, unsigned int page_size,