diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-07-18 14:28:21 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-07-25 16:47:15 +0000 |
| commit | a327a6763a356dc386c0f273fe091784a20b495a (patch) | |
| tree | ac7f4ef68fee25df16f5019f84f43d843f4105a6 /src/cpu/testers/traffic_gen/dram_rot_gen.hh | |
| parent | 2fe3d660260e7b546b5860ac4459014ed9bee907 (diff) | |
| download | gem5-a327a6763a356dc386c0f273fe091784a20b495a.tar.xz | |
cpu: Allow creation of traffic gen from generic SimObjects
This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.
Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/testers/traffic_gen/dram_rot_gen.hh')
| -rw-r--r-- | src/cpu/testers/traffic_gen/dram_rot_gen.hh | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.hh b/src/cpu/testers/traffic_gen/dram_rot_gen.hh index 9c9a6ce05..59a1bc2fa 100644 --- a/src/cpu/testers/traffic_gen/dram_rot_gen.hh +++ b/src/cpu/testers/traffic_gen/dram_rot_gen.hh @@ -66,11 +66,13 @@ class DramRotGen : public DramGen * 2) Command type (if applicable) * 3) Ranks per channel * - * @param gen Traffic generator owning this sequence generator + * @param obj SimObject owning this sequence generator + * @param master_id MasterID related to the memory requests * @param _duration duration of this state before transitioning * @param start_addr Start address * @param end_addr End address * @param _blocksize Size used for transactions injected + * @param cacheline_size cache line size in the system * @param min_period Lower limit of random inter-transaction time * @param max_period Upper limit of random inter-transaction time * @param read_percent Percent of transactions that are reads @@ -85,8 +87,9 @@ class DramRotGen : public DramGen * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo * assumes single channel system */ - DramRotGen(BaseTrafficGen &gen, Tick _duration, - Addr start_addr, Addr end_addr, Addr _blocksize, + DramRotGen(SimObject &obj, MasterID master_id, Tick _duration, + Addr start_addr, Addr end_addr, + Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, @@ -94,8 +97,9 @@ class DramRotGen : public DramGen unsigned int addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank) - : DramGen(gen, _duration, start_addr, end_addr, - _blocksize, min_period, max_period, read_percent, data_limit, + : DramGen(obj, master_id, _duration, start_addr, end_addr, + _blocksize, cacheline_size, min_period, max_period, + read_percent, data_limit, num_seq_pkts, page_size, nbr_of_banks_DRAM, nbr_of_banks_util, addr_mapping, nbr_of_ranks), |