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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:32 -0400 |
| commit | 6279eaf1f7d28b370ede16d52475a7da372d2dde (patch) | |
| tree | a3d645dbf7a2b44ceeefbacf5f191ba2e55223b2 /src/cpu/testers/traffic_gen/generators.cc | |
| parent | ac42db8134bff8617e20e1a034dc0d65158335ae (diff) | |
| download | gem5-6279eaf1f7d28b370ede16d52475a7da372d2dde.tar.xz | |
mem: Use STL deque in favour of list for DRAM queues
This patch changes the data structure used for the DRAM read, write
and response queues from an STL list to deque. This optimisation is
based on the observation that the size is small (and fixed), and that
the structures are frequently iterated over in a linear fashion.
Diffstat (limited to 'src/cpu/testers/traffic_gen/generators.cc')
0 files changed, 0 insertions, 0 deletions