cpu: DRAM Traffic Generator

This patch enables a new 'DRAM' mode to the existing traffic
generator, catered to generate specific requests to DRAM based on
required hit length (stride size) and bank utilization. It is an add on
to the Random mode.

The basic idea is to control how many successive packets target the
same page, and how many banks are being used in parallel. This gives a
two-dimensional space that stresses different aspects of the DRAM
timing.

The configuration file needed to use this patch has to be changed as
follow: (reference to Random Mode, LPDDR3 memory type)

'STATE 0 10000000000 RANDOM 50 0 134217728 64 3004 5002 0'
-> 'STATE 0 10000000000 DRAM 50 0 134217728 32 3004 5002 0 96 1024 8 6 1'

The last 4 parameters to be added are:
<stride size (bytes), page size(bytes), number of banks available in DRAM,
    number of banks to be utilized, address mapping scheme>

The address mapping information is used to get the stride address
stream of the specified size and to know where to find the bank
bits. The configuration file has a parameter where '0'-> RoCoRaBaCh,
'1'-> RoRaBaCoCh/RoRaBaChCo address-mapping schemes. Note that the
generator currently assumes a single channel and a single rank. This
is to avoid overwhelming the traffic generator with information about
the memory organisation.

1 files changed, 52 insertions, 2 deletions

diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc
index 4b2259bd9..d53c9b000 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -41,6 +41,7 @@
 
 #include <sstream>
 
+#include "base/intmath.hh"
 #include "base/random.hh"
 #include "cpu/testers/traffic_gen/traffic_gen.hh"
 #include "debug/Checkpoint.hh"
@@ -257,7 +258,8 @@ TrafficGen::parseConfig()
                 } else if (mode == "IDLE") {
                     states[id] = new IdleGen(name(), masterID, duration);
                     DPRINTF(TrafficGen, "State: %d IdleGen\n", id);
-                } else if (mode == "LINEAR" || mode == "RANDOM") {
+                } else if (mode == "LINEAR" || mode == "RANDOM" ||
+                           mode == "DRAM") {
                     uint32_t read_percent;
                     Addr start_addr;
                     Addr end_addr;
@@ -277,7 +279,7 @@ TrafficGen::parseConfig()
 
                     if (blocksize > system->cacheLineSize())
                         fatal("TrafficGen %s block size (%d) is larger than "
-                              "system block size (%d)\n", name(),
+                              "cache line size (%d)\n", name(),
                               blocksize, system->cacheLineSize());
 
                     if (read_percent > 100)
@@ -300,6 +302,54 @@ TrafficGen::parseConfig()
                                                    min_period, max_period,
                                                    read_percent, data_limit);
                         DPRINTF(TrafficGen, "State: %d RandomGen\n", id);
+                    } else if (mode == "DRAM") {
+                        // stride size (bytes) of the request for achieving
+                        // required hit length
+                        unsigned int stride_size;
+                        unsigned int page_size;
+                        unsigned int nbr_of_banks_DRAM;
+                        unsigned int nbr_of_banks_util;
+                        unsigned int addr_mapping;
+
+                        is >> stride_size >> page_size >> nbr_of_banks_DRAM >>
+                            nbr_of_banks_util >> addr_mapping;
+
+                        if (stride_size > page_size)
+                            warn("DRAM generator stride size (%d) is greater "
+                                 "than page size (%d)  of the memory\n",
+                                 blocksize, page_size);
+
+                        if (nbr_of_banks_util > nbr_of_banks_DRAM)
+                            fatal("Attempting to use more banks (%) than "
+                                  "what is available (%)\n",
+                                  nbr_of_banks_util, nbr_of_banks_DRAM);
+
+                        if (nbr_of_banks_util > nbr_of_banks_DRAM)
+                            fatal("Attempting to use more banks (%) than "
+                                  "what is available (%)\n",
+                                  nbr_of_banks_util, nbr_of_banks_DRAM);
+
+                        // count the number of sequential packets to
+                        // generate
+                        unsigned int num_seq_pkts = 1;
+
+                        if (stride_size > blocksize) {
+                            num_seq_pkts = divCeil(stride_size, blocksize);
+                            DPRINTF(TrafficGen, "stride size: %d "
+                                    "block size: %d, num_seq_pkts: %d\n",
+                                    stride_size, blocksize, num_seq_pkts);
+                        }
+
+                        states[id] = new DramGen(name(), masterID,
+                                                 duration, start_addr,
+                                                 end_addr, blocksize,
+                                                 min_period, max_period,
+                                                 read_percent, data_limit,
+                                                 num_seq_pkts, page_size,
+                                                 nbr_of_banks_DRAM,
+                                                 nbr_of_banks_util,
+                                                 addr_mapping);
+                        DPRINTF(TrafficGen, "State: %d DramGen\n", id);
                     }
                 } else {
                     fatal("%s: Unknown traffic generator mode: %s",