MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

4 files changed, 6 insertions, 5 deletions

diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index ccadc5b36..bf3eace08 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -48,6 +48,6 @@ class InvalidateGenerator(DirectedGenerator):
 
 class RubyDirectedTester(MemObject):
     type = 'RubyDirectedTester'
-    cpuPort = VectorPort("the cpu ports")
+    cpuPort = VectorMasterPort("the cpu ports")
     requests_to_complete = Param.Int("checks to complete")
     generator = Param.DirectedGenerator("the request generator")
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index 6a3568379..1b4d6767c 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -48,8 +48,9 @@ class MemTest(MemObject):
         "progress report interval (in accesses)")
     trace_addr = Param.Addr(0, "address to trace")
 
-    test = Port("Port to the memory system to test")
-    functional = Port("Port to the functional memory used for verification")
+    test = MasterPort("Port to the memory system to test")
+    functional = MasterPort("Port to the functional memory " \
+                                "used for verification")
     suppress_func_warnings = Param.Bool(False,
         "suppress warnings when functional accesses fail.\n")
     sys = Param.System(Parent.any, "System Parameter")
diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py
index b2eda9aa2..7d6ed576b 100644
--- a/src/cpu/testers/networktest/NetworkTest.py
+++ b/src/cpu/testers/networktest/NetworkTest.py
@@ -41,5 +41,5 @@ class NetworkTest(MemObject):
     traffic_type = Param.Counter(0, "Traffic type: uniform random, tornado, bit complement")
     inj_rate = Param.Float(0.1, "Packet injection rate")
     precision = Param.Int(3, "Number of digits of precision after decimal point")
-    test = Port("Port to the memory system to test")
+    test = MasterPort("Port to the memory system to test")
     system = Param.System(Parent.any, "System we belong to")
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index fc0a60e11..6518862e9 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -32,7 +32,7 @@ from m5.proxy import *
 
 class RubyTester(MemObject):
     type = 'RubyTester'
-    cpuPort = VectorPort("the cpu ports")
+    cpuPort = VectorMasterPort("the cpu ports")
     checks_to_complete = Param.Int(100, "checks to complete")
     deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
     wakeup_frequency = Param.Int(10, "number of cycles between wakeups")