summaryrefslogtreecommitdiff
path: root/src/cpu/testers
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-07-18 08:31:16 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-07-18 08:31:16 -0400
commitd4273cc9a6f3c00566e97ebcd71509ed14477b37 (patch)
tree9b50625fc5d2bb457a959f379a45687903660237 /src/cpu/testers
parent4e8ecd7c6fd0447f563179b5a8fdbb13b562ca9e (diff)
downloadgem5-d4273cc9a6f3c00566e97ebcd71509ed14477b37.tar.xz
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
Diffstat (limited to 'src/cpu/testers')
-rw-r--r--src/cpu/testers/memtest/memtest.cc11
-rw-r--r--src/cpu/testers/traffic_gen/traffic_gen.cc7
2 files changed, 8 insertions, 10 deletions
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 37684ec5d..7f3ff0d03 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -95,7 +95,7 @@ MemTest::MemTest(const Params *p)
tickEvent(this),
cachePort("test", this),
funcPort("functional", this),
- funcProxy(funcPort),
+ funcProxy(funcPort, p->sys->cacheLineSize()),
retryPkt(NULL),
// mainMem(main_mem),
// checkMem(check_mem),
@@ -105,6 +105,7 @@ MemTest::MemTest(const Params *p)
percentUncacheable(p->percent_uncacheable),
issueDmas(p->issue_dmas),
masterId(p->sys->getMasterId(name())),
+ blockSize(p->sys->cacheLineSize()),
progressInterval(p->progress_interval),
nextProgressMessage(p->progress_interval),
percentSourceUnaligned(p->percent_source_unaligned),
@@ -121,6 +122,9 @@ MemTest::MemTest(const Params *p)
baseAddr2 = 0x400000;
uncacheAddr = 0x800000;
+ blockAddrMask = blockSize - 1;
+ traceBlockAddr = blockAddr(traceBlockAddr);
+
// set up counters
noResponseCycles = 0;
numReads = 0;
@@ -145,11 +149,6 @@ MemTest::getMasterPort(const std::string &if_name, PortID idx)
void
MemTest::init()
{
- // By the time init() is called, the ports should be hooked up.
- blockSize = cachePort.peerBlockSize();
- blockAddrMask = blockSize - 1;
- traceBlockAddr = blockAddr(traceBlockAddr);
-
// initial memory contents for both physical memory and functional
// memory should be 0; no need to initialize them.
}
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc
index ed3518bb4..0f006e67e 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.cc
+++ b/src/cpu/testers/traffic_gen/traffic_gen.cc
@@ -268,11 +268,10 @@ TrafficGen::parseConfig()
max_period, read_percent);
- if (port.deviceBlockSize() &&
- blocksize > port.deviceBlockSize())
+ if (blocksize > system->cacheLineSize())
fatal("TrafficGen %s block size (%d) is larger than "
- "port block size (%d)\n", name(),
- blocksize, port.deviceBlockSize());
+ "system block size (%d)\n", name(),
+ blocksize, system->cacheLineSize());
if (read_percent > 100)
fatal("%s cannot have more than 100% reads", name());