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authorAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:01 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:01 -0400
commit2308f812ef848d027b99dd52c0900aed11260d87 (patch)
tree8f2dfe7b5345e74eb1b0b3ebb7417a5587ba5395 /src/cpu/testers
parente82996d9dad5ac38fe2c8709c05b26cf92d356e8 (diff)
downloadgem5-2308f812ef848d027b99dd52c0900aed11260d87.tar.xz
mem: Make the buses multi layered
This patch makes the buses multi layered, and effectively creates a crossbar structure with distributed contention ports at the destination ports. Before this patch, a bus could have a single request, response and snoop response in flight at any time, and with these changes there can be as many requests as connected slaves (bus master ports), and as many responses as connected masters (bus slave ports). Together with address interleaving, this patch enables us to create high-throughput memory interconnects, e.g. 50+ GByte/s.
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