MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

8 files changed, 51 insertions, 58 deletions

diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc
index 4518066eb..bfdd28e08 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.cc
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc
@@ -75,19 +75,19 @@ RubyDirectedTester::init()
     generator->setDirectedTester(this);
 }
 
-Port *
-RubyDirectedTester::getPort(const std::string &if_name, int idx)
+MasterPort &
+RubyDirectedTester::getMasterPort(const std::string &if_name, int idx)
 {
     if (if_name != "cpuPort") {
-        panic("RubyDirectedTester::getPort: unknown port %s requested",
-              if_name);
-    }
+        // pass it along to our super class
+        return MemObject::getMasterPort(if_name, idx);
+    } else {
+        if (idx >= static_cast<int>(ports.size())) {
+            panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
+        }
 
-    if (idx >= static_cast<int>(ports.size())) {
-        panic("RubyDirectedTester::getPort: unknown index %d requested\n", idx);
+        return *ports[idx];
     }
-
-    return ports[idx];
 }
 
 Tick
@@ -110,7 +110,7 @@ RubyDirectedTester::CpuPort::recvTiming(PacketPtr pkt)
     return true;
 }
 
-Port*
+MasterPort*
 RubyDirectedTester::getCpuPort(int idx)
 {
     assert(idx >= 0 && idx < ports.size());
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh
index cd0632976..cb207ff80 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.hh
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh
@@ -47,7 +47,7 @@ class DirectedGenerator;
 class RubyDirectedTester : public MemObject
 {
   public:
-    class CpuPort : public Port
+    class CpuPort : public MasterPort
     {
       private:
         RubyDirectedTester *tester;
@@ -55,25 +55,27 @@ class RubyDirectedTester : public MemObject
       public:
         CpuPort(const std::string &_name, RubyDirectedTester *_tester,
                 uint32_t _idx)
-            : Port(_name, _tester), tester(_tester), idx(_idx)
+            : MasterPort(_name, _tester), tester(_tester), idx(_idx)
         {}
 
         uint32_t idx;
 
       protected:
         virtual bool recvTiming(PacketPtr pkt);
+        virtual void recvRetry()
+        { panic("%s does not expect a retry\n", name()); }
         virtual Tick recvAtomic(PacketPtr pkt);
         virtual void recvFunctional(PacketPtr pkt) { }
-        virtual void recvRangeChange() { }
     };
 
     typedef RubyDirectedTesterParams Params;
     RubyDirectedTester(const Params *p);
     ~RubyDirectedTester();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
-    Port* getCpuPort(int idx);
+    MasterPort* getCpuPort(int idx);
 
     virtual void init();
 
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index dffaa71ed..07cdf73a6 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -85,11 +85,6 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
 }
 
 void
-MemTest::CpuPort::recvRangeChange()
-{
-}
-
-void
 MemTest::CpuPort::recvRetry()
 {
     memtest->doRetry();
@@ -161,15 +156,15 @@ MemTest::MemTest(const Params *p)
     dmaOutstanding = false;
 }
 
-Port *
-MemTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+MemTest::getMasterPort(const std::string &if_name, int idx)
 {
     if (if_name == "functional")
-        return &funcPort;
+        return funcPort;
     else if (if_name == "test")
-        return &cachePort;
+        return cachePort;
     else
-        panic("No Such Port\n");
+        return MemObject::getMasterPort(if_name, idx);
 }
 
 void
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index c56a37574..d179fa530 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -62,7 +62,8 @@ class MemTest : public MemObject
     // main simulation loop (one cycle)
     void tick();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
     /**
      * Print state of address in memory system via PrintReq (for
@@ -84,14 +85,14 @@ class MemTest : public MemObject
 
     TickEvent tickEvent;
 
-    class CpuPort : public Port
+    class CpuPort : public MasterPort
     {
         MemTest *memtest;
 
       public:
 
         CpuPort(const std::string &_name, MemTest *_memtest)
-            : Port(_name, _memtest), memtest(_memtest)
+            : MasterPort(_name, _memtest), memtest(_memtest)
         { }
 
       protected:
@@ -102,8 +103,6 @@ class MemTest : public MemObject
 
         virtual void recvFunctional(PacketPtr pkt);
 
-        virtual void recvRangeChange();
-
         virtual void recvRetry();
     };
 
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 3fe153c4e..01f247707 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -82,11 +82,6 @@ NetworkTest::CpuPort::recvFunctional(PacketPtr pkt)
 }
 
 void
-NetworkTest::CpuPort::recvRangeChange()
-{
-}
-
-void
 NetworkTest::CpuPort::recvRetry()
 {
     networktest->doRetry();
@@ -126,13 +121,13 @@ NetworkTest::NetworkTest(const Params *p)
             name(), id);
 }
 
-Port *
-NetworkTest::getPort(const std::string &if_name, int idx)
+MasterPort &
+NetworkTest::getMasterPort(const std::string &if_name, int idx)
 {
     if (if_name == "test")
-        return &cachePort;
+        return cachePort;
     else
-        panic("No Such Port\n");
+        return MemObject::getMasterPort(if_name, idx);
 }
 
 void
diff --git a/src/cpu/testers/networktest/networktest.hh b/src/cpu/testers/networktest/networktest.hh
index de67d41a0..21984f45d 100644
--- a/src/cpu/testers/networktest/networktest.hh
+++ b/src/cpu/testers/networktest/networktest.hh
@@ -57,7 +57,8 @@ class NetworkTest : public MemObject
     // main simulation loop (one cycle)
     void tick();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
     /**
      * Print state of address in memory system via PrintReq (for
@@ -79,14 +80,14 @@ class NetworkTest : public MemObject
 
     TickEvent tickEvent;
 
-    class CpuPort : public Port
+    class CpuPort : public MasterPort
     {
         NetworkTest *networktest;
 
       public:
 
         CpuPort(const std::string &_name, NetworkTest *_networktest)
-            : Port(_name, _networktest), networktest(_networktest)
+            : MasterPort(_name, _networktest), networktest(_networktest)
         { }
 
       protected:
@@ -97,8 +98,6 @@ class NetworkTest : public MemObject
 
         virtual void recvFunctional(PacketPtr pkt);
 
-        virtual void recvRangeChange();
-
         virtual void recvRetry();
     };
 
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index 70ee40aed..e1942cf61 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -92,18 +92,19 @@ RubyTester::init()
     m_checkTable_ptr = new CheckTable(m_num_cpu_sequencers, this);
 }
 
-Port *
-RubyTester::getPort(const std::string &if_name, int idx)
+MasterPort &
+RubyTester::getMasterPort(const std::string &if_name, int idx)
 {
     if (if_name != "cpuPort") {
-        panic("RubyTester::getPort: unknown port %s requested\n", if_name);
-    }
+        // pass it along to our super class
+        return MemObject::getMasterPort(if_name, idx);
+    } else {
+        if (idx >= static_cast<int>(ports.size())) {
+            panic("RubyTester::getMasterPort: unknown index %d\n", idx);
+        }
 
-    if (idx >= static_cast<int>(ports.size())) {
-        panic("RubyTester::getPort: unknown index %d requested\n", idx);
+        return *ports[idx];
     }
-
-    return ports[idx];
 }
 
 Tick
@@ -135,7 +136,7 @@ RubyTester::CpuPort::recvTiming(PacketPtr pkt)
     return true;
 }
 
-Port*
+MasterPort*
 RubyTester::getCpuPort(int idx)
 {
     assert(idx >= 0 && idx < ports.size());
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index e8cf4c874..b24dddd83 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -45,23 +45,24 @@
 class RubyTester : public MemObject
 {
   public:
-    class CpuPort : public Port
+    class CpuPort : public MasterPort
     {
       private:
         RubyTester *tester;
 
       public:
         CpuPort(const std::string &_name, RubyTester *_tester, int _idx)
-            : Port(_name, _tester), tester(_tester), idx(_idx)
+            : MasterPort(_name, _tester), tester(_tester), idx(_idx)
         {}
 
         int idx;
 
       protected:
         virtual bool recvTiming(PacketPtr pkt);
+        virtual void recvRetry()
+        { panic("%s does not expect a retry\n", name()); }
         virtual Tick recvAtomic(PacketPtr pkt);
         virtual void recvFunctional(PacketPtr pkt) { }
-        virtual void recvRangeChange() { }
     };
 
     struct SenderState : public Packet::SenderState
@@ -86,9 +87,10 @@ class RubyTester : public MemObject
     RubyTester(const Params *p);
     ~RubyTester();
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
-    Port* getCpuPort(int idx);
+    MasterPort* getCpuPort(int idx);
 
     virtual void init();