mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.

15 files changed, 39 insertions, 15 deletions

diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc
index 68ea55449..d69261cf0 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -28,9 +28,11 @@
  */
 
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
+#include "sim/system.hh"
 
 DirectedGenerator::DirectedGenerator(const Params *p)
-    : SimObject(p)
+    : SimObject(p),
+      masterId(p->system->getMasterId(name()))
 {
     m_num_cpus = p->num_cpus;
     m_directed_tester = NULL;
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh
index c156efff0..422a0ddb6 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -49,6 +49,7 @@ class DirectedGenerator : public SimObject
     
   protected:
     int m_num_cpus;
+    MasterID masterId;
     RubyDirectedTester* m_directed_tester;
 };
 
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index 4d8271a05..f01e6fb50 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -58,7 +58,7 @@ InvalidateGenerator::initiate()
     Packet::Command cmd;
 
     // For simplicity, requests are assumed to be 1 byte-sized
-    Request *req = new Request(m_address, 1, flags);
+    Request *req = new Request(m_address, 1, flags, masterId);
 
     //
     // Based on the current state, issue a load or a store
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index af1970594..ccadc5b36 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -35,6 +35,7 @@ class DirectedGenerator(SimObject):
     type = 'DirectedGenerator'
     abstract = True
     num_cpus = Param.Int("num of cpus")
+    system = Param.System(Parent.any, "System we belong to")
 
 class SeriesRequestGenerator(DirectedGenerator):
     type = 'SeriesRequestGenerator'
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 4cf9aed1c..137d24b21 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -59,7 +59,7 @@ SeriesRequestGenerator::initiate()
     Request::Flags flags;
 
     // For simplicity, requests are assumed to be 1 byte-sized
-    Request *req = new Request(m_address, 1, flags);
+    Request *req = new Request(m_address, 1, flags, masterId);
 
     Packet::Command cmd;
     if (m_issue_writes) {
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index d5f456d69..6a3568379 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -52,3 +52,5 @@ class MemTest(MemObject):
     functional = Port("Port to the functional memory used for verification")
     suppress_func_warnings = Param.Bool(False,
         "suppress warnings when functional accesses fail.\n")
+    sys = Param.System(Parent.any, "System Parameter")
+
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index d70dc96e6..2d0131a92 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -46,6 +46,7 @@
 #include "mem/request.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
+#include "sim/system.hh"
 
 using namespace std;
 
@@ -132,6 +133,7 @@ MemTest::MemTest(const Params *p)
       percentFunctional(p->percent_functional),
       percentUncacheable(p->percent_uncacheable),
       issueDmas(p->issue_dmas),
+      masterId(p->sys->getMasterId(name())),
       progressInterval(p->progress_interval),
       nextProgressMessage(p->progress_interval),
       percentSourceUnaligned(p->percent_source_unaligned),
@@ -321,11 +323,11 @@ MemTest::tick()
 
     if (issueDmas) {
         paddr &= ~((1 << dma_access_size) - 1);
-        req->setPhys(paddr, 1 << dma_access_size, flags);
+        req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
         req->setThreadContext(id,0);
     } else {
         paddr &= ~((1 << access_size) - 1);
-        req->setPhys(paddr, 1 << access_size, flags);
+        req->setPhys(paddr, 1 << access_size, flags, masterId);
         req->setThreadContext(id,0);
     }
     assert(req->getSize() == 1);
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index 1a59914fd..208b34caf 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -138,6 +138,9 @@ class MemTest : public MemObject
 
     bool issueDmas;
 
+    /** Request id for all generated traffic */
+    MasterID masterId;
+
     int id;
 
     std::set<unsigned> outstandingAddrs;
diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py
index 0a18ca938..b2eda9aa2 100644
--- a/src/cpu/testers/networktest/NetworkTest.py
+++ b/src/cpu/testers/networktest/NetworkTest.py
@@ -28,6 +28,7 @@
 
 from MemObject import MemObject
 from m5.params import *
+from m5.proxy import *
 
 class NetworkTest(MemObject):
     type = 'NetworkTest'
@@ -41,3 +42,4 @@ class NetworkTest(MemObject):
     inj_rate = Param.Float(0.1, "Packet injection rate")
     precision = Param.Int(3, "Number of digits of precision after decimal point")
     test = Port("Port to the memory system to test")
+    system = Param.System(Parent.any, "System we belong to")
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 56fcc46c4..3fe153c4e 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -44,6 +44,7 @@
 #include "mem/request.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
+#include "sim/system.hh"
 
 using namespace std;
 
@@ -113,7 +114,8 @@ NetworkTest::NetworkTest(const Params *p)
       maxPackets(p->max_packets),
       trafficType(p->traffic_type),
       injRate(p->inj_rate),
-      precision(p->precision)
+      precision(p->precision),
+      masterId(p->system->getMasterId(name()))
 {
     // set up counters
     noResponseCycles = 0;
@@ -263,17 +265,17 @@ NetworkTest::generatePkt()
     if (randomReqType == 0) {
         // generate packet for virtual network 0
         requestType = MemCmd::ReadReq;
-        req->setPhys(paddr, access_size, flags);
+        req->setPhys(paddr, access_size, flags, masterId);
     } else if (randomReqType == 1) {
         // generate packet for virtual network 1
         requestType = MemCmd::ReadReq;
         flags.set(Request::INST_FETCH);
-        req->setVirt(0, 0x0, access_size, flags, 0x0);
+        req->setVirt(0, 0x0, access_size, flags, 0x0, masterId);
         req->setPaddr(paddr);
     } else {  // if (randomReqType == 2)
         // generate packet for virtual network 2
         requestType = MemCmd::WriteReq;
-        req->setPhys(paddr, access_size, flags);
+        req->setPhys(paddr, access_size, flags, masterId);
     }
 
     req->setThreadContext(id,0);
diff --git a/src/cpu/testers/networktest/networktest.hh b/src/cpu/testers/networktest/networktest.hh
index c277cfbab..de67d41a0 100644
--- a/src/cpu/testers/networktest/networktest.hh
+++ b/src/cpu/testers/networktest/networktest.hh
@@ -134,6 +134,8 @@ class NetworkTest : public MemObject
     double injRate;
     int precision;
 
+    MasterID masterId;
+
     void completeRequest(PacketPtr pkt);
 
     void generatePkt();
diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index 164fb56e1..2444a14ab 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -103,8 +103,8 @@ Check::initiatePrefetch()
     }
 
     // Prefetches are assumed to be 0 sized
-    Request *req = new Request(m_address.getAddress(), 0, flags, curTick(),
-                               m_pc.getAddress());
+    Request *req = new Request(m_address.getAddress(), 0, flags,
+            m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
     req->setThreadContext(index, 0);
 
     PacketPtr pkt = new Packet(req, cmd, port->idx);
@@ -141,8 +141,8 @@ Check::initiateFlush()
 
     Request::Flags flags;
 
-    Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(),
-                               m_pc.getAddress());
+    Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
+            m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
 
     Packet::Command cmd;
 
@@ -176,7 +176,8 @@ Check::initiateAction()
     Address writeAddr(m_address.getAddress() + m_store_count);
 
     // Stores are assumed to be 1 byte-sized
-    Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(),
+    Request *req = new Request(writeAddr.getAddress(), 1, flags,
+            m_tester_ptr->masterId(), curTick(),
                                m_pc.getAddress());
 
     req->setThreadContext(index, 0);
@@ -243,7 +244,7 @@ Check::initiateCheck()
 
     // Checks are sized depending on the number of bytes written
     Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
-                               curTick(), m_pc.getAddress());
+                               m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
 
     req->setThreadContext(index, 0);
     PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc
index 5040d9fae..81bb93253 100644
--- a/src/cpu/testers/rubytest/RubyTester.cc
+++ b/src/cpu/testers/rubytest/RubyTester.cc
@@ -36,9 +36,11 @@
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/system/System.hh"
 #include "sim/sim_exit.hh"
+#include "sim/system.hh"
 
 RubyTester::RubyTester(const Params *p)
   : MemObject(p), checkStartEvent(this),
+    _masterId(p->system->getMasterId(name())),
     m_checks_to_complete(p->checks_to_complete),
     m_deadlock_threshold(p->deadlock_threshold),
     m_wakeup_frequency(p->wakeup_frequency),
diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh
index 1c0147c7e..fae40a417 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -101,6 +101,7 @@ class RubyTester : public MemObject
     void print(std::ostream& out) const;
     bool getCheckFlush() { return m_check_flush; }
 
+    MasterID masterId() { return _masterId; }
   protected:
     class CheckStartEvent : public Event
     {
@@ -117,6 +118,8 @@ class RubyTester : public MemObject
 
     CheckStartEvent checkStartEvent;
 
+    MasterID _masterId;
+
   private:
     void hitCallback(NodeID proc, SubBlock* data);
 
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index fd6e9aefd..fc0a60e11 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -37,3 +37,4 @@ class RubyTester(MemObject):
     deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
     wakeup_frequency = Param.Int(10, "number of cycles between wakeups")
     check_flush = Param.Bool(False, "check cache flushing")
+    system = Param.System(Parent.any, "System we belong to")