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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-03 13:10:26 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
commit | 2113b21996d086dab32b9fd388efe3df241bfbd2 (patch) | |
tree | 26d944027f726dde3ec49b67538663ccc41bcad3 /src/cpu/testers | |
parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
download | gem5-2113b21996d086dab32b9fd388efe3df241bfbd2.tar.xz |
misc: Substitute pointer to Request with aliased RequestPtr
Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.
Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/cpu/testers')
-rw-r--r-- | src/cpu/testers/directedtest/InvalidateGenerator.cc | 2 | ||||
-rw-r--r-- | src/cpu/testers/directedtest/SeriesRequestGenerator.cc | 2 | ||||
-rw-r--r-- | src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc | 4 | ||||
-rw-r--r-- | src/cpu/testers/memtest/memtest.cc | 4 | ||||
-rw-r--r-- | src/cpu/testers/rubytest/Check.cc | 8 | ||||
-rw-r--r-- | src/cpu/testers/traffic_gen/base_gen.cc | 2 |
6 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index c5c48f1ad..3319e8400 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -60,7 +60,7 @@ InvalidateGenerator::initiate() Packet::Command cmd; // For simplicity, requests are assumed to be 1 byte-sized - Request *req = new Request(m_address, 1, flags, masterId); + RequestPtr req = new Request(m_address, 1, flags, masterId); // // Based on the current state, issue a load or a store diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index 386a49893..17ae04cdf 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -60,7 +60,7 @@ SeriesRequestGenerator::initiate() Request::Flags flags; // For simplicity, requests are assumed to be 1 byte-sized - Request *req = new Request(m_address, 1, flags, masterId); + RequestPtr req = new Request(m_address, 1, flags, masterId); Packet::Command cmd; bool do_write = (random_mt.random(0, 100) < m_percent_writes); diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc index 56edd842b..be1921aad 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc @@ -129,7 +129,7 @@ GarnetSyntheticTraffic::init() void GarnetSyntheticTraffic::completeRequest(PacketPtr pkt) { - Request *req = pkt->req; + RequestPtr req = pkt->req; DPRINTF(GarnetSyntheticTraffic, "Completed injection of %s packet for address %x\n", @@ -279,7 +279,7 @@ GarnetSyntheticTraffic::generatePkt() // MemCmd::Command requestType; - Request *req = nullptr; + RequestPtr req = nullptr; Request::Flags flags; // Inject in specific Vnet diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index ccd978c94..89b4d1159 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -136,7 +136,7 @@ MemTest::getMasterPort(const std::string &if_name, PortID idx) void MemTest::completeRequest(PacketPtr pkt, bool functional) { - Request *req = pkt->req; + RequestPtr req = pkt->req; assert(req->getSize() == 1); // this address is no longer outstanding @@ -246,7 +246,7 @@ MemTest::tick() bool do_functional = (random_mt.random(0, 100) < percentFunctional) && !uncacheable; - Request *req = new Request(paddr, 1, flags, masterId); + RequestPtr req = new Request(paddr, 1, flags, masterId); req->setContext(id); outstandingAddrs.insert(paddr); diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc index 2ce79e72d..776d711a2 100644 --- a/src/cpu/testers/rubytest/Check.cc +++ b/src/cpu/testers/rubytest/Check.cc @@ -107,7 +107,7 @@ Check::initiatePrefetch() } // Prefetches are assumed to be 0 sized - Request *req = new Request(m_address, 0, flags, + RequestPtr req = new Request(m_address, 0, flags, m_tester_ptr->masterId(), curTick(), m_pc); req->setContext(index); @@ -146,7 +146,7 @@ Check::initiateFlush() Request::Flags flags; - Request *req = new Request(m_address, CHECK_SIZE, flags, + RequestPtr req = new Request(m_address, CHECK_SIZE, flags, m_tester_ptr->masterId(), curTick(), m_pc); Packet::Command cmd; @@ -179,7 +179,7 @@ Check::initiateAction() Addr writeAddr(m_address + m_store_count); // Stores are assumed to be 1 byte-sized - Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(), + RequestPtr req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(), curTick(), m_pc); req->setContext(index); @@ -244,7 +244,7 @@ Check::initiateCheck() } // Checks are sized depending on the number of bytes written - Request *req = new Request(m_address, CHECK_SIZE, flags, + RequestPtr req = new Request(m_address, CHECK_SIZE, flags, m_tester_ptr->masterId(), curTick(), m_pc); req->setContext(index); diff --git a/src/cpu/testers/traffic_gen/base_gen.cc b/src/cpu/testers/traffic_gen/base_gen.cc index cd568f151..b5b4f5817 100644 --- a/src/cpu/testers/traffic_gen/base_gen.cc +++ b/src/cpu/testers/traffic_gen/base_gen.cc @@ -59,7 +59,7 @@ BaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd, Request::FlagsType flags) { // Create new request - Request *req = new Request(addr, size, flags, masterID); + RequestPtr req = new Request(addr, size, flags, masterID); // Dummy PC to have PC-based prefetchers latch on; get entropy into higher // bits req->setPC(((Addr)masterID) << 2); |