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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-03 14:25:52 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-03 14:25:52 -0500 |
| commit | 5ea60a95b3d87fac6723678e07822aed512f966e (patch) | |
| tree | a104cbcc0e4f15deb4ad87f6642a16ca1145ab0e /src/cpu/thread_context.cc | |
| parent | 9aad5b45690adae9f1208b6d3cc8dfc670d54543 (diff) | |
| download | gem5-5ea60a95b3d87fac6723678e07822aed512f966e.tar.xz | |
config: Adjust DRAM channel interleaving defaults
This patch changes the DRAM channel interleaving default behaviour to
be more representative. The default address mapping (RoRaBaCoCh) moves
the channel bits towards the least significant bits, and uses 128 byte
as the default channel interleaving granularity.
These defaults can be overridden if desired, but should serve as a
sensible starting point for most use-cases.
Diffstat (limited to 'src/cpu/thread_context.cc')
0 files changed, 0 insertions, 0 deletions