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| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/cpu/thread_context.cc | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/thread_context.cc')
| -rw-r--r-- | src/cpu/thread_context.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 7597dbfb2..3f5781b32 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -71,8 +71,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) // Then loop through the floating point registers. for (int i = 0; i < TheISA::NumFloatRegs; ++i) { - RegVal t1 = one->readFloatRegBits(i); - RegVal t2 = two->readFloatRegBits(i); + RegVal t1 = one->readFloatReg(i); + RegVal t2 = two->readFloatReg(i); if (t1 != t2) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -169,7 +169,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp) RegVal floatRegs[NumFloatRegs]; for (int i = 0; i < NumFloatRegs; ++i) - floatRegs[i] = tc.readFloatRegBitsFlat(i); + floatRegs[i] = tc.readFloatRegFlat(i); // This is a bit ugly, but needed to maintain backwards // compatibility. arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); @@ -213,7 +213,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) // compatibility. arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); for (int i = 0; i < NumFloatRegs; ++i) - tc.setFloatRegBitsFlat(i, floatRegs[i]); + tc.setFloatRegFlat(i, floatRegs[i]); std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); UNSERIALIZE_CONTAINER(vecRegs); |