cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

1 files changed, 6 insertions, 18 deletions

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index efa0b2162..43c40481e 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -250,19 +250,16 @@ class ThreadContext
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
-    virtual int flattenIntIndex(int reg) = 0;
-    virtual int flattenFloatIndex(int reg) = 0;
-    virtual int flattenCCIndex(int reg) = 0;
-    virtual int flattenMiscIndex(int reg) = 0;
+    virtual RegId flattenRegId(const RegId& regId) const = 0;
 
     virtual uint64_t
-    readRegOtherThread(RegId misc_reg, ThreadID tid)
+    readRegOtherThread(const RegId& misc_reg, ThreadID tid)
     {
         return 0;
     }
 
     virtual void
-    setRegOtherThread(RegId misc_reg, const MiscReg &val, ThreadID tid)
+    setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid)
     {
     }
 
@@ -291,7 +288,7 @@ class ThreadContext
      *
      * Some architectures have different registers visible in
      * different modes. Such architectures "flatten" a register (see
-     * flattenIntIndex() and flattenFloatIndex()) to map it into the
+     * flattenRegId()) to map it into the
      * gem5 register file. This interface provides a flat interface to
      * the underlying register file, which allows for example
      * serialization code to access all registers.
@@ -466,17 +463,8 @@ class ProxyThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
-    int flattenIntIndex(int reg)
-    { return actualTC->flattenIntIndex(reg); }
-
-    int flattenFloatIndex(int reg)
-    { return actualTC->flattenFloatIndex(reg); }
-
-    int flattenCCIndex(int reg)
-    { return actualTC->flattenCCIndex(reg); }
-
-    int flattenMiscIndex(int reg)
-    { return actualTC->flattenMiscIndex(reg); }
+    RegId flattenRegId(const RegId& regId) const
+    { return actualTC->flattenRegId(regId); }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }