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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
commit | f85286b3debf4a4a94d3b959e5bb880be81bd692 (patch) | |
tree | 56a6be55a52d6cc6bb7e5d92fdcb25c79ad7d196 /src/cpu/thread_context.hh | |
parent | 06c39a154c4dc8fedcf9fbf77bbcf26f176c469c (diff) | |
download | gem5-f85286b3debf4a4a94d3b959e5bb880be81bd692.tar.xz |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r-- | src/cpu/thread_context.hh | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 3b7f8b3c3..d80d26e3d 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -50,9 +50,9 @@ class BaseCPU; class Checkpoint; class Decoder; class EndQuiesceEvent; -class TranslatingPort; -class FunctionalPort; -class VirtualPort; +class SETranslatingPortProxy; +class FSTranslatingPortProxy; +class PortProxy; class Process; class System; namespace TheISA { @@ -128,13 +128,19 @@ class ThreadContext #if FULL_SYSTEM virtual TheISA::Kernel::Statistics *getKernelStats() = 0; - virtual FunctionalPort *getPhysPort() = 0; + virtual PortProxy* getPhysProxy() = 0; - virtual VirtualPort *getVirtPort() = 0; + virtual FSTranslatingPortProxy* getVirtProxy() = 0; - virtual void connectMemPorts(ThreadContext *tc) = 0; + /** + * Initialise the physical and virtual port proxies and tie them to + * the data port of the CPU. + * + * tc ThreadContext for the virtual-to-physical translation + */ + virtual void initMemProxies(ThreadContext *tc) = 0; #else - virtual TranslatingPort *getMemPort() = 0; + virtual SETranslatingPortProxy *getMemProxy() = 0; virtual Process *getProcessPtr() = 0; #endif @@ -298,13 +304,13 @@ class ProxyThreadContext : public ThreadContext TheISA::Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } - FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } + PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } - VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } + FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } - void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } + void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } #else - TranslatingPort *getMemPort() { return actualTC->getMemPort(); } + SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } Process *getProcessPtr() { return actualTC->getProcessPtr(); } #endif |