cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.

1 files changed, 24 insertions, 0 deletions

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index dbe3c0ce8..be18f680f 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -96,6 +97,7 @@ class ThreadContext
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
+    typedef TheISA::CCReg CCReg;
     typedef TheISA::MiscReg MiscReg;
   public:
 
@@ -200,12 +202,16 @@ class ThreadContext
 
     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 
+    virtual CCReg readCCReg(int reg_idx) = 0;
+
     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 
     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 
+    virtual void setCCReg(int reg_idx, CCReg val) = 0;
+
     virtual TheISA::PCState pcState() = 0;
 
     virtual void pcState(const TheISA::PCState &val) = 0;
@@ -228,6 +234,7 @@ class ThreadContext
 
     virtual int flattenIntIndex(int reg) = 0;
     virtual int flattenFloatIndex(int reg) = 0;
+    virtual int flattenCCIndex(int reg) = 0;
 
     virtual uint64_t
     readRegOtherThread(int misc_reg, ThreadID tid)
@@ -283,6 +290,8 @@ class ThreadContext
     virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
     virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
 
+    virtual CCReg readCCRegFlat(int idx) = 0;
+    virtual void setCCRegFlat(int idx, CCReg val) = 0;
     /** @} */
 
 };
@@ -391,6 +400,9 @@ class ProxyThreadContext : public ThreadContext
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
+    CCReg readCCReg(int reg_idx)
+    { return actualTC->readCCReg(reg_idx); }
+
     void setIntReg(int reg_idx, uint64_t val)
     { actualTC->setIntReg(reg_idx, val); }
 
@@ -400,6 +412,9 @@ class ProxyThreadContext : public ThreadContext
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     { actualTC->setFloatRegBits(reg_idx, val); }
 
+    void setCCReg(int reg_idx, CCReg val)
+    { actualTC->setCCReg(reg_idx, val); }
+
     TheISA::PCState pcState() { return actualTC->pcState(); }
 
     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
@@ -433,6 +448,9 @@ class ProxyThreadContext : public ThreadContext
     int flattenFloatIndex(int reg)
     { return actualTC->flattenFloatIndex(reg); }
 
+    int flattenCCIndex(int reg)
+    { return actualTC->flattenCCIndex(reg); }
+
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
 
@@ -464,6 +482,12 @@ class ProxyThreadContext : public ThreadContext
 
     void setFloatRegBitsFlat(int idx, FloatRegBits val)
     { actualTC->setFloatRegBitsFlat(idx, val); }
+
+    CCReg readCCRegFlat(int idx)
+    { return actualTC->readCCRegFlat(idx); }
+
+    void setCCRegFlat(int idx, CCReg val)
+    { actualTC->setCCRegFlat(idx, val); }
 };
 
 /** @{ */