Registers: Add an ISA object which replaces the MiscRegFile.

This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.

1 files changed, 9 insertions, 1 deletions

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3e37572d8..8963553d5 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -84,7 +84,6 @@ class ThreadContext
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
   public:
 
@@ -234,6 +233,9 @@ class ThreadContext
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
+    virtual int flattenIntIndex(int reg) = 0;
+    virtual int flattenFloatIndex(int reg) = 0;
+
     virtual uint64_t
     readRegOtherThread(int misc_reg, ThreadID tid)
     {
@@ -434,6 +436,12 @@ class ProxyThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
+    int flattenIntIndex(int reg)
+    { return actualTC->flattenIntIndex(reg); }
+
+    int flattenFloatIndex(int reg)
+    { return actualTC->flattenFloatIndex(reg); }
+
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }