arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

1 files changed, 3 insertions, 2 deletions

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index bb6b54c08..efa0b2162 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -51,6 +51,7 @@
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
+#include "cpu/reg_class.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
@@ -255,13 +256,13 @@ class ThreadContext
     virtual int flattenMiscIndex(int reg) = 0;
 
     virtual uint64_t
-    readRegOtherThread(int misc_reg, ThreadID tid)
+    readRegOtherThread(RegId misc_reg, ThreadID tid)
     {
         return 0;
     }
 
     virtual void
-    setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
+    setRegOtherThread(RegId misc_reg, const MiscReg &val, ThreadID tid)
     {
     }