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authorGabe Black <gblack@eecs.umich.edu>2011-09-09 02:30:01 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-09-09 02:30:01 -0700
commitb7b545bc38bcd9ee54f1b8e45064cd8b7a3070b0 (patch)
treee81962e78194fa13c768e6a841f367bd71dd5c83 /src/cpu/thread_context.hh
parentc5fd6f4fec147dbdbbd46794bdbbf5782ea7a57d (diff)
downloadgem5-b7b545bc38bcd9ee54f1b8e45064cd8b7a3070b0.tar.xz
Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r--src/cpu/thread_context.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 0f7228f0c..3b7f8b3c3 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -48,6 +48,7 @@ namespace TheISA
}
class BaseCPU;
class Checkpoint;
+class Decoder;
class EndQuiesceEvent;
class TranslatingPort;
class FunctionalPort;
@@ -120,6 +121,8 @@ class ThreadContext
virtual TheISA::TLB *getDTBPtr() = 0;
+ virtual Decoder *getDecoderPtr() = 0;
+
virtual System *getSystemPtr() = 0;
#if FULL_SYSTEM
@@ -287,6 +290,8 @@ class ProxyThreadContext : public ThreadContext
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+
System *getSystemPtr() { return actualTC->getSystemPtr(); }
#if FULL_SYSTEM