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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-16 03:33:28 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-16 03:33:28 -0500 |
| commit | d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51 (patch) | |
| tree | f990864e7fb9ffaf11e3895e8337737941390aa2 /src/cpu/thread_context.hh | |
| parent | 07ce60bdfa57eedf00f533704b5a2da3fa01b553 (diff) | |
| download | gem5-d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51.tar.xz | |
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
Diffstat (limited to 'src/cpu/thread_context.hh')
| -rw-r--r-- | src/cpu/thread_context.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 850ff9468..966924c50 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -225,7 +225,7 @@ class ThreadContext virtual MicroPC microPC() = 0; - virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; + virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; virtual MiscReg readMiscReg(int misc_reg) = 0; @@ -429,7 +429,7 @@ class ProxyThreadContext : public ThreadContext void setPredicate(bool val) { actualTC->setPredicate(val); } - MiscReg readMiscRegNoEffect(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) const { return actualTC->readMiscRegNoEffect(misc_reg); } MiscReg readMiscReg(int misc_reg) |