summaryrefslogtreecommitdiff
path: root/src/cpu/thread_context.hh
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-04-08 22:21:27 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-08 22:21:27 -0700
commit7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch)
tree4c212f665de2628eac6f84d389de7a79b6d0b933 /src/cpu/thread_context.hh
parent08043c777f1f05f5e14581950013461f328965be (diff)
downloadgem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r--src/cpu/thread_context.hh11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 700f1571e..72c9df33d 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -44,8 +44,7 @@
// DTB pointers.
namespace TheISA
{
- class DTB;
- class ITB;
+ class TLB;
}
class BaseCPU;
class EndQuiesceEvent;
@@ -124,9 +123,9 @@ class ThreadContext
virtual void setContextId(int id) = 0;
- virtual TheISA::ITB *getITBPtr() = 0;
+ virtual TheISA::TLB *getITBPtr() = 0;
- virtual TheISA::DTB *getDTBPtr() = 0;
+ virtual TheISA::TLB *getDTBPtr() = 0;
virtual System *getSystemPtr() = 0;
@@ -306,9 +305,9 @@ class ProxyThreadContext : public ThreadContext
void setContextId(int id) { actualTC->setContextId(id); }
- TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
+ TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
- TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
System *getSystemPtr() { return actualTC->getSystemPtr(); }