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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
| commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
| tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/thread_context.hh | |
| parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
| download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz | |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/thread_context.hh')
| -rw-r--r-- | src/cpu/thread_context.hh | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index cd8b98f0c..2544b19c6 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -98,7 +98,6 @@ class ThreadContext typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; - typedef TheISA::VectorReg VectorReg; typedef TheISA::MiscReg MiscReg; public: @@ -206,8 +205,6 @@ class ThreadContext virtual CCReg readCCReg(int reg_idx) = 0; - virtual const VectorReg &readVectorReg(int reg_idx) = 0; - virtual void setIntReg(int reg_idx, uint64_t val) = 0; virtual void setFloatReg(int reg_idx, FloatReg val) = 0; @@ -216,8 +213,6 @@ class ThreadContext virtual void setCCReg(int reg_idx, CCReg val) = 0; - virtual void setVectorReg(int reg_idx, const VectorReg &val) = 0; - virtual TheISA::PCState pcState() = 0; virtual void pcState(const TheISA::PCState &val) = 0; @@ -241,7 +236,6 @@ class ThreadContext virtual int flattenIntIndex(int reg) = 0; virtual int flattenFloatIndex(int reg) = 0; virtual int flattenCCIndex(int reg) = 0; - virtual int flattenVectorIndex(int reg) = 0; virtual int flattenMiscIndex(int reg) = 0; virtual uint64_t @@ -297,9 +291,6 @@ class ThreadContext virtual CCReg readCCRegFlat(int idx) = 0; virtual void setCCRegFlat(int idx, CCReg val) = 0; - - virtual const VectorReg &readVectorRegFlat(int idx) = 0; - virtual void setVectorRegFlat(int idx, const VectorReg &val) = 0; /** @} */ }; @@ -411,9 +402,6 @@ class ProxyThreadContext : public ThreadContext CCReg readCCReg(int reg_idx) { return actualTC->readCCReg(reg_idx); } - const VectorReg &readVectorReg(int reg_idx) - { return actualTC->readVectorReg(reg_idx); } - void setIntReg(int reg_idx, uint64_t val) { actualTC->setIntReg(reg_idx, val); } @@ -426,9 +414,6 @@ class ProxyThreadContext : public ThreadContext void setCCReg(int reg_idx, CCReg val) { actualTC->setCCReg(reg_idx, val); } - void setVectorReg(int reg_idx, const VectorReg &val) - { actualTC->setVectorReg(reg_idx, val); } - TheISA::PCState pcState() { return actualTC->pcState(); } void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } @@ -465,9 +450,6 @@ class ProxyThreadContext : public ThreadContext int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } - int flattenVectorIndex(int reg) - { return actualTC->flattenVectorIndex(reg); } - int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } @@ -505,12 +487,6 @@ class ProxyThreadContext : public ThreadContext void setCCRegFlat(int idx, CCReg val) { actualTC->setCCRegFlat(idx, val); } - - const VectorReg &readVectorRegFlat(int idx) - { return actualTC->readVectorRegFlat(idx); } - - void setVectorRegFlat(int idx, const VectorReg &val) - { actualTC->setVectorRegFlat(idx, val); } }; /** @{ */ |