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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-23 13:26:30 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-23 13:26:30 -0700 |
| commit | 245b0bd9b94bfaaa188b7e945f91c0e4a9909cbe (patch) | |
| tree | 7ca0de263839f60d35cd6cf0ca8c17d94c375209 /src/cpu/thread_context.hh | |
| parent | 57ff2604e59647c6afe988767186f13c80c1aa16 (diff) | |
| parent | ac19e0c5050219cbb0579a319fa3fab5cf92835d (diff) | |
| download | gem5-245b0bd9b94bfaaa188b7e945f91c0e4a9909cbe.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
--HG--
extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
Diffstat (limited to 'src/cpu/thread_context.hh')
| -rw-r--r-- | src/cpu/thread_context.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 05c409c95..3706d8543 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -234,6 +234,10 @@ class ThreadContext virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } + + virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; + // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. virtual unsigned readStCondFailures() = 0; |