cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 24 insertions, 0 deletions

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 2544b19c6..cd8b98f0c 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -98,6 +98,7 @@ class ThreadContext
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::CCReg CCReg;
+    typedef TheISA::VectorReg VectorReg;
     typedef TheISA::MiscReg MiscReg;
   public:
 
@@ -205,6 +206,8 @@ class ThreadContext
 
     virtual CCReg readCCReg(int reg_idx) = 0;
 
+    virtual const VectorReg &readVectorReg(int reg_idx) = 0;
+
     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 
     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
@@ -213,6 +216,8 @@ class ThreadContext
 
     virtual void setCCReg(int reg_idx, CCReg val) = 0;
 
+    virtual void setVectorReg(int reg_idx, const VectorReg &val) = 0;
+
     virtual TheISA::PCState pcState() = 0;
 
     virtual void pcState(const TheISA::PCState &val) = 0;
@@ -236,6 +241,7 @@ class ThreadContext
     virtual int flattenIntIndex(int reg) = 0;
     virtual int flattenFloatIndex(int reg) = 0;
     virtual int flattenCCIndex(int reg) = 0;
+    virtual int flattenVectorIndex(int reg) = 0;
     virtual int flattenMiscIndex(int reg) = 0;
 
     virtual uint64_t
@@ -291,6 +297,9 @@ class ThreadContext
 
     virtual CCReg readCCRegFlat(int idx) = 0;
     virtual void setCCRegFlat(int idx, CCReg val) = 0;
+
+    virtual const VectorReg &readVectorRegFlat(int idx) = 0;
+    virtual void setVectorRegFlat(int idx, const VectorReg &val) = 0;
     /** @} */
 
 };
@@ -402,6 +411,9 @@ class ProxyThreadContext : public ThreadContext
     CCReg readCCReg(int reg_idx)
     { return actualTC->readCCReg(reg_idx); }
 
+    const VectorReg &readVectorReg(int reg_idx)
+    { return actualTC->readVectorReg(reg_idx); }
+
     void setIntReg(int reg_idx, uint64_t val)
     { actualTC->setIntReg(reg_idx, val); }
 
@@ -414,6 +426,9 @@ class ProxyThreadContext : public ThreadContext
     void setCCReg(int reg_idx, CCReg val)
     { actualTC->setCCReg(reg_idx, val); }
 
+    void setVectorReg(int reg_idx, const VectorReg &val)
+    { actualTC->setVectorReg(reg_idx, val); }
+
     TheISA::PCState pcState() { return actualTC->pcState(); }
 
     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
@@ -450,6 +465,9 @@ class ProxyThreadContext : public ThreadContext
     int flattenCCIndex(int reg)
     { return actualTC->flattenCCIndex(reg); }
 
+    int flattenVectorIndex(int reg)
+    { return actualTC->flattenVectorIndex(reg); }
+
     int flattenMiscIndex(int reg)
     { return actualTC->flattenMiscIndex(reg); }
 
@@ -487,6 +505,12 @@ class ProxyThreadContext : public ThreadContext
 
     void setCCRegFlat(int idx, CCReg val)
     { actualTC->setCCRegFlat(idx, val); }
+
+    const VectorReg &readVectorRegFlat(int idx)
+    { return actualTC->readVectorRegFlat(idx); }
+
+    void setVectorRegFlat(int idx, const VectorReg &val)
+    { actualTC->setVectorRegFlat(idx, val); }
 };
 
 /** @{ */