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authorGabe Black <gabeblack@google.com>2019-10-09 21:32:11 -0700
committerGabe Black <gabeblack@google.com>2019-10-25 22:42:31 +0000
commit74a66d8e6706ccaed79facc6df3999f7dee2075a (patch)
treec1b03caf8419a65240ef5451b839b5a7e2765043 /src/cpu/thread_context.hh
parent2b7d4bd73db443b4ca302213689a673266e856e0 (diff)
downloadgem5-74a66d8e6706ccaed79facc6df3999f7dee2075a.tar.xz
cpu: Make the ThreadContext a PCEventScope.
Both the thread and system's PCEventQueue are checked when appropriate. Change-Id: I16c371339c91a37b5641860d974e546a30e23e13 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/cpu/thread_context.hh')
-rw-r--r--src/cpu/thread_context.hh3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 0bd29302b..749b4ca90 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -51,6 +51,7 @@
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
+#include "cpu/pc_event.hh"
#include "cpu/reg_class.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
@@ -88,7 +89,7 @@ namespace Kernel {
* interface; the ExecContext is a more implicit interface that must
* be implemented so that the ISA can access whatever state it needs.
*/
-class ThreadContext
+class ThreadContext : public PCEventScope
{
protected:
typedef TheISA::MachInst MachInst;