Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.

src/cpu/base_dyn_inst.cc:
    Delete the allocated data in destructor.
src/cpu/base_dyn_inst.hh:
    Only copy the addresses if the translation succeeded.
src/cpu/o3/alpha_cpu.hh:
    Return actual translating port.
    Don't panic on setNextNPC() as it's always called, regardless of the architecture, when the process initializes.
src/cpu/o3/alpha_cpu_impl.hh:
    Pass in memobject to the thread state in SE mode.
src/cpu/o3/commit_impl.hh:
    Initialize all variables.
src/cpu/o3/decode_impl.hh:
    Handle early resolution of branches properly.
src/cpu/o3/fetch.hh:
    Switch structure back to requests.
src/cpu/o3/fetch_impl.hh:
    Initialize all variables, create/delete requests properly.
src/cpu/o3/lsq_unit.hh:
    Include sender state along with the packet.  Also include a more generic writeback event that's only used for stores forwarding data to loads.
src/cpu/o3/lsq_unit_impl.hh:
    Redo writeback code to support the response path of the memory system.
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit_impl.hh:
    Wrap variables in #ifdefs.
src/cpu/o3/store_set.cc:
    Include to get panic() function.
src/cpu/o3/thread_state.hh:
    Create with MemObject as well.
src/cpu/thread_state.hh:
    Have a translating port in the thread state object.
src/python/m5/objects/AlphaFullCPU.py:
    Mem parameter no longer needed.

--HG--
extra : convert_revision : a99381fb25cb183322882ce20935a6f3d1f2b64d

1 files changed, 20 insertions, 6 deletions

diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index e09cb12fd..a96884d5b 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -31,6 +31,10 @@
 
 #include "cpu/exec_context.hh"
 
+#if !FULL_SYSTEM
+#include "mem/translating_port.hh"
+#endif
+
 #if FULL_SYSTEM
 class EndQuiesceEvent;
 class FunctionProfile;
@@ -51,17 +55,27 @@ class Process;
  */
 struct ThreadState {
 #if FULL_SYSTEM
-    ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem)
-        : cpuId(_cpuId), tid(_tid), mem(_mem), lastActivate(0), lastSuspend(0),
+    ThreadState(int _cpuId, int _tid)
+        : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
           profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL)
 #else
-    ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem,
+    ThreadState(int _cpuId, int _tid, MemObject *mem,
                 Process *_process, short _asid)
-        : cpuId(_cpuId), tid(_tid), mem(_mem), process(_process), asid(_asid)
+        : cpuId(_cpuId), tid(_tid), process(_process), asid(_asid)
 #endif
     {
         funcExeInst = 0;
         storeCondFailures = 0;
+#if !FULL_SYSTEM
+        /* Use this port to for syscall emulation writes to memory. */
+        Port *mem_port;
+        port = new TranslatingPort(csprintf("%d-funcport",
+                                            tid),
+                                   process->pTable, false);
+        mem_port = mem->getPort("functional");
+        mem_port->setPeer(port);
+        port->setPeer(mem_port);
+#endif
     }
 
     ExecContext::Status status;
@@ -79,8 +93,6 @@ struct ThreadState {
     Counter numLoad;
     Counter startNumLoad;
 
-    FunctionalMemory *mem;	// functional storage for process address space
-
 #if FULL_SYSTEM
     Tick lastActivate;
     Tick lastSuspend;
@@ -93,6 +105,8 @@ struct ThreadState {
 
     Kernel::Statistics *kernelStats;
 #else
+    TranslatingPort *port;
+
     Process *process;
 
     // Address space ID.  Note that this is used for TIMING cache