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author | Curtis Dunham <Curtis.Dunham@arm.com> | 2017-05-18 21:30:37 +0000 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:24:03 +0000 |
commit | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (patch) | |
tree | c246f14a22a9efd00eff6243d6ae996f58af4657 /src/cpu/timing_expr.cc | |
parent | e1c8c1f8603672823c89e5ed4c98502350c600d6 (diff) | |
download | gem5-864f87f9c56a66dceeca0f4e9470fbaa3001b627.tar.xz |
arm,kvm: update CP15 timer model when exiting Kvm
The ARM MiscRegs implementation has two interfaces: 'normal'
and 'no effect'. The latter acts as a way to access the
backing store without architectural 'effects'. For instance,
a normal write to a timer compare value would call into the
timer model to emulate the device. The 'no effect' interface,
however, would just write the value into the register backing
store and do nothing else.
For Kvm execution, a delicate balance must be struck for the
timer device specifically. We need the code in the model
to be run, because it contains state other than the register
backing store that must stay in sync. On the other hand, we
don't necessarily want the timer model to schedule gem5
events when this happens.
In this commit, we ensure that we use the 'effectful'
MiscReg interface when copying the CP15 timer registers
from Kvm back into gem5. The prior commit makes sure
that this doesn't generate unnecessary timer events
or interrupts.
Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9
Reviewed-on: https://gem5-review.googlesource.com/3543
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/timing_expr.cc')
0 files changed, 0 insertions, 0 deletions