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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-06-09 23:18:46 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-06-09 23:18:46 -0400 |
| commit | 95019d0c6f1675f42d899f2899e06d3017088f25 (patch) | |
| tree | 7618cd95da8299faff8dd682e088ee707cae6a7f /src/cpu/trace/opt_cpu.cc | |
| parent | 6de5d73a999240f92f050393bb10028968275835 (diff) | |
| parent | 29e34a739b991af8d8e1eafe75ecb0904c324dc8 (diff) | |
| download | gem5-95019d0c6f1675f42d899f2899e06d3017088f25.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem
into vm1.(none):/home/stever/bk/newmem-py
src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
Hand merge.
--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf
Diffstat (limited to 'src/cpu/trace/opt_cpu.cc')
| -rw-r--r-- | src/cpu/trace/opt_cpu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/trace/opt_cpu.cc b/src/cpu/trace/opt_cpu.cc index 098031d4a..996e89f01 100644 --- a/src/cpu/trace/opt_cpu.cc +++ b/src/cpu/trace/opt_cpu.cc @@ -176,7 +176,7 @@ OptCPU::tick() fprintf(stderr,"sys.cpu.misses %d #opt cache misses\n",misses); fprintf(stderr,"sys.cpu.hits %d #opt cache hits\n", hits); fprintf(stderr,"sys.cpu.accesses %d #opt cache acceses\n", references); - new SimExitEvent("Finshed Memory Trace"); + exitSimLoop("end of memory trace reached"); } void |