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| author | Nathan Binkert <nate@binkert.org> | 2007-07-26 23:15:49 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2007-07-26 23:15:49 -0700 |
| commit | f0fef8f850b0c5aa73337ca11b26169163b2b2e1 (patch) | |
| tree | d49d3492618ee85717554cddbe62cba1b5e7fb9c /src/cpu/trace/trace_cpu.cc | |
| parent | 6b73ff43ff58502c80050c7aeff5a08a4ce61f87 (diff) | |
| parent | cda354b07035f73a3b220f89014721300d36a815 (diff) | |
| download | gem5-f0fef8f850b0c5aa73337ca11b26169163b2b2e1.tar.xz | |
Merge python and x86 changes with cache branch
--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
Diffstat (limited to 'src/cpu/trace/trace_cpu.cc')
| -rw-r--r-- | src/cpu/trace/trace_cpu.cc | 28 |
1 files changed, 4 insertions, 24 deletions
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index 32ed6c7d7..e5739b2ce 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -40,7 +40,7 @@ #include "cpu/trace/reader/mem_trace_reader.hh" #include "mem/base_mem.hh" // For PARAM constructor #include "mem/mem_interface.hh" -#include "sim/builder.hh" +#include "params/TraceCPU.hh" #include "sim/sim_events.hh" using namespace std; @@ -151,31 +151,11 @@ TraceCPU::TickEvent::description() return "TraceCPU tick"; } - - -BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU) - - SimObjectParam<BaseMem *> icache; - SimObjectParam<BaseMem *> dcache; - SimObjectParam<MemTraceReader *> data_trace; - -END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU) - -BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU) - - INIT_PARAM_DFLT(icache, "instruction cache", NULL), - INIT_PARAM_DFLT(dcache, "data cache", NULL), - INIT_PARAM_DFLT(data_trace, "data trace", NULL) - -END_INIT_SIM_OBJECT_PARAMS(TraceCPU) - -CREATE_SIM_OBJECT(TraceCPU) +TraceCPU * +TraceCPUParams::create() { - return new TraceCPU(getInstanceName(), + return new TraceCPU(name, (icache) ? icache->getInterface() : NULL, (dcache) ? dcache->getInterface() : NULL, data_trace); } - -REGISTER_SIM_OBJECT("TraceCPU", TraceCPU) - |