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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
commit | c75ff71139d6358678835cca63e35d1135eaf466 (patch) | |
tree | 0811177db4dca4a237b8e5d7dd65f8ec155cb14e /src/cpu/trace | |
parent | d99deff8ea296fd28b48da08aba577a1e7dfc01b (diff) | |
download | gem5-c75ff71139d6358678835cca63e35d1135eaf466.tar.xz |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
Diffstat (limited to 'src/cpu/trace')
-rw-r--r-- | src/cpu/trace/trace_cpu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index d6aa9aaeb..e81a79818 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -627,7 +627,7 @@ TraceCPU::ElasticDataGen::executeMemReq(GraphNode* node_ptr) // Create a request and the packet containing request Request* req = new Request(node_ptr->physAddr, node_ptr->size, node_ptr->flags, masterID, node_ptr->seqNum, - ContextID(0), ThreadID(0)); + ContextID(0)); req->setPC(node_ptr->pc); // If virtual address is valid, set the asid and virtual address fields // of the request. @@ -1123,7 +1123,7 @@ TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd, req->setPC(pc); // If this is not done it triggers assert in L1 cache for invalid contextId - req->setThreadContext(ContextID(0), ThreadID(0)); + req->setContext(ContextID(0)); // Embed it in a packet PacketPtr pkt = new Packet(req, cmd); |