Merge vm1.(none):/home/stever/bk/newmem

into  vm1.(none):/home/stever/bk/newmem-py

src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
    Hand merge.

--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf

2 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/trace/opt_cpu.cc b/src/cpu/trace/opt_cpu.cc
index 098031d4a..996e89f01 100644
--- a/src/cpu/trace/opt_cpu.cc
+++ b/src/cpu/trace/opt_cpu.cc
@@ -176,7 +176,7 @@ OptCPU::tick()
     fprintf(stderr,"sys.cpu.misses %d #opt cache misses\n",misses);
     fprintf(stderr,"sys.cpu.hits %d #opt cache hits\n", hits);
     fprintf(stderr,"sys.cpu.accesses %d #opt cache acceses\n", references);
-    new SimExitEvent("Finshed Memory Trace");
+    exitSimLoop("end of memory trace reached");
 }
 
 void
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 4df47229f..3c9da4849 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -108,7 +108,7 @@ TraceCPU::tick()
     if (!nextReq) {
         // No more requests to send. Finish trailing events and exit.
         if (mainEventQueue.empty()) {
-            new SimExitEvent("Finshed Memory Trace");
+            exitSimLoop("end of memory trace reached");
         } else {
             tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
         }